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ENEE 359a
Lecture/s 9
Transistor Sizing
Bruce Jacob
University of
Maryland
ECE Dept.
ENEE 359a
Digital VLSI Design
SLIDE 1
Transistor Sizing
& Logical Effort
Prof. Bruce Jacob
[email protected]
Credit where credit is due:
Slides contain original artwork (© Jacob 2004) as well as material taken liberally
from Irwin & Vijay’s CSE477 slides (PSU), Schmit & Strojwas’s 18-322 slides
(CMU), Dally’s EE273 slides (Stanford), Wolf’s slides for Modern VLSI Design,
and/or Rabaey’s slides (UCB).
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Overview
Bruce Jacob
University of
Maryland
ECE Dept.
•
Sizing of transistors to balance
performance of single inverter
•
More on RC time constant, first-order
approximation of time delays
•
Sizing in complex gates, examples
•
Sizing of inverter chains for driving high
capacitance loads (off-chip wires)
SLIDE 2
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Resistance
Bruce Jacob
University of
Maryland
ECE Dept.
WOULD LIKE BALANCED NETWORKS:
VDD
SLIDE 3
“Dual” networks
Pull-up
Network
(pFET network)
INPUT/S
OUTPUT
Pull-down
Network
(nFET network)
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Resistance
Bruce Jacob
University of
Maryland
ECE Dept.
Resistance of MOSFET:
1
L

R n = ---------------------------------------------- ----µ n C ox ( V GS – V Tn )  W 
SLIDE 4
•
Increasing W decreases the resistance;
allows more current to flow
Oxide capacitance C ox = ε ox ⁄ t ox [F/cm2]
Gate capacitance C G = C ox WL [F]
W
W
Transconductance β n = µ n C ox  ----- = k' n  -----
 L
 L
(units [A/V2])
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Resistance
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 5
nFET vs. pFET
1
R n = ------------------------------------β n ( V DD – V Tn )
1
R p = ---------------------------------------β p ( V DD – V Tp )
µn
----- = r
µp
W

β n = µ n C ox ---- Ln
W
β p = µ p C ox  -----
 Lp
Typically
(2 .. 3)
(µ is the carrier mobility through device)
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Transistor Sizing
Bruce Jacob
University of
Maryland
ECE Dept.
SIMPLE CASE: Inverter
VDD
VDD
SLIDE 6
Rp
CL
VOUT
VOUT
CL
CL
Rn
Charging: Vout rising
Discharging: Vout falling
If (W/L)p = r(W/L)n then ßn = ßp
(and Rn = Rp)
… symmetric inverter
Make pFET bigger (wider) by factor of r
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Transistor Sizing
Bruce Jacob
University of
Maryland
ECE Dept.
SIMPLE CASE: Inverter
VDD
VDD
SLIDE 7
Rp
CL
VOUT
VOUT
CL
CL
Rn
Charging: Vout rising
Discharging: Vout falling
tpLH = ln(2) Rp CL = 0.69 Rp CL
tpHL = ln(2) Rn CL = 0.69 Rn CL
tp = (tpHL + tpLH)/2 = 0.69 CL(Rn + Rp)/2
(note: the ln(2)RC term comes from first-order analysis of simple
RC circuit’s respose to step input ... time for output to reach 50% value
… more detail on this in a moment, after we discuss capacitance …)
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Wire Resistance
Bruce Jacob
l
University of
Maryland
ECE Dept.
w
r
h
SLIDE 8
•
•
UNIVERSITY OF MARYLAND
l
R = ρl/A = ρl/(wh) for rectangular wires
(on-chip wires & vias, PCB traces)
πr2) for circular wires
R = ρl/A = ρl/(π
(off-chip, off-PCB)
Material
Ω-m)
Resistivity ρ (Ω
Silver (Ag)
1.6 x 10-8
Copper (Cu)
1.7 x 10-8
Gold (Au)
2.2 x 10-8
Aluminum (Al)
2.7 x 10-8
Tungsten (W)
5.5 x 10-8
ENEE 359a
Lecture/s 9
Transistor Sizing
Sheet Resistance
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 9
ρ/h for rectangular wires
R = ρl/(wh) = l/w•ρ
Sheet resistance Rsq = ρ/h (h=thickness)
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Material
Ω/sq)
Sheet resistance Rsq (Ω
n, p well diffusion
1000 to 1500
n+, p+ diffusion
50 to 150
polysilicon
150 to 200
polysilicon with silicide
4 to 5
Aluminum
0.05 to 0.1
ENEE 359a
Lecture/s 9
Transistor Sizing
More on Resistance
Bruce Jacob
University of
Maryland
ECE Dept.
Sheet resistance Rsq
SLIDE 10
12 squares
6 squares
= 1sq + 1sq + 0.56sq
UNIVERSITY OF MARYLAND
= 1sq + 1sq + 0.2sq
ENEE 359a
Lecture/s 9
Transistor Sizing
More on Resistance
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 11
(it’s not just the channel that counts)
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
And Now … Capacitance (CL)
Bruce Jacob
University of
Maryland
ECE Dept.
Vin
Vout
Vin
Vout2
CL
SLIDE 12
M2
Vin
Vin
CGD12
UNIVERSITY OF MARYLAND
M4
CDB2
Vout2
Vout
pdrain
ndrain
M1
•
•
•
CG4
Cw
CDB1
M3
CG3
intrinsic MOS transistor capacitances
extrinsic MOS transistor (fanout) capacitances
wiring (interconnect) capacitance
ENEE 359a
Lecture/s 9
Transistor Sizing
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 13
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CW, a Large Example
ENEE 359a
Lecture/s 9
Transistor Sizing
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 14
UNIVERSITY OF MARYLAND
CW, a Large Example
ENEE 359a
Lecture/s 9
Transistor Sizing
Two Chained Inverters
Bruce Jacob
University of
Maryland
ECE Dept.
VDD
PMOS
1.125/0.25
SLIDE 15
1.2µm
λ
=2λ
In
Out
Metal1
Polysilicon
0.125 spacing
NMOS
0.375/0.25
UNIVERSITY OF MARYLAND
GND
0.5 width
ENEE 359a
Lecture/s 9
Transistor Sizing
Bruce Jacob
University of
Maryland
ECE Dept.
Gate-Drain Capacitance CGD
VDD
PMOS
1.125/0.25
SLIDE 16
1.2µm
λ
=2λ
Out
In
Metal1
Polysilicon
NMOS
0.375/0.25
poly
0.125 spacing
SiO2
Scales with transistor width W
UNIVERSITY OF MARYLAND
GND
0.5 width
Overlaps
ENEE 359a
Lecture/s 9
Transistor Sizing
Bruce Jacob
Diffusion Capacitance CDB
VDD
University of
Maryland
ECE Dept.
PMOS
1.125/0.25
SLIDE 17
1.2µm
λ
=2λ
Out
In
Metal1
Polysilicon
NMOS
0.375/0.25
•
UNIVERSITY OF MARYLAND
Reverse-Biased
P/N Junction
p+
GND
n-doped substrate or well
Drain is reverse-biased diode, non-linear C dependent
on drain voltage (approx. nonlinearity with linear eqn,
using K terms for bottom plate and sidewalls)
ENEE 359a
Lecture/s 9
Transistor Sizing
Bruce Jacob
University of
Maryland
ECE Dept.
Gate/Fan-out Capacitance CG
VDD
PMOS
1.125/0.25
SLIDE 18
1.2µm
λ
=2λ
Out
In
Metal1
Polysilicon
poly
SiO
2
NMOS
0.125 spacing
0.375/0.25
0.5 widthPlate
Overlaps + Parallel
Scales with both W and L
UNIVERSITY OF MARYLAND
GND
ENEE 359a
Lecture/s 9
Transistor Sizing
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 19
Two Chained Inverters: CL
C Term Expression
Value (fF) Value (fF)
H→L
L→H
CGD1
2 Con Wn
0.23
0.23
CGD2
2 Cop Wp
0.61
0.61
CDB1
KeqbpnADnCj + KeqswnPDnCjsw 0.66
0.90
CDB2
KeqbppADpCj + KeqswpPDpCjsw 1.50
1.15
CG3
2 Con Wn + Cox Wn Ln
0.76
0.76
CG4
2 Cop Wp + Cox Wp Lp
2.28
2.28
CW
From extraction
0.12
0.12
CL
Sum
6.1
6.0
•
•
UNIVERSITY OF MARYLAND
Terms in red: under control of designer
CL split between intrinsic and extrinsic/wire sources
ENEE 359a
Lecture/s 9
Transistor Sizing
MOSFET Switching
Bruce Jacob
University of
Maryland
ECE Dept.
Parallel switching (all switch at same time):
VDD
A
B
C
SLIDE 20
t PLH
Rp
= 0.7 • ------- • ( N • C oxp + C load )
N
Cload
Series switching (all switch at same time):
A
B
C
UNIVERSITY OF MARYLAND
Cload
t PHL = 0.35 • R n C oxn • N
2
+ 0.7 • N • R n • C load
ENEE 359a
Lecture/s 9
Transistor Sizing
RC Delay, Two Inverters
Bruce Jacob
3
2.5
SLIDE 21
2
Vout (V)
University of
Maryland
ECE Dept.
Vin
1.5
tpHL
1
tf
tr
tpLH
0.5
0
-0.5
0
•
•
•
•
UNIVERSITY OF MARYLAND
0.5
1
VDD=2.5V, 0.25mm
W/Ln = 1.5, W/Lp = 4.5
Ω (÷ 1.5)
Reqn= 13 kΩ
Ω (÷ 4.5)
Reqp= 31 kΩ
t (sec)
1.5
2
2.5x 10
-10
tpHL = 0.69 RnC = 36 ps
tpLH = 0.69 RpC = 29 ps
From SPICE simulation:
tpHL = 39.9 ps, tpLH = 31.7 ps
ENEE 359a
Lecture/s 9
Transistor Sizing
Transistor Sizing I
Bruce Jacob
University of
Maryland
ECE Dept.
W
SLIDE 22
Source
2W
L
L
Drain
The electrical characteristics of transistors
determine the switching speed of a circuit
•
Need to select the aspect ratios (W/L)n and (W/L)p of
every FET in the circuit
Define Unit Transistor (R1, C1)
•
•
•
•
UNIVERSITY OF MARYLAND
L/Wmin-> highest resistance (needs scaling)
R2= R1 ÷ 2 and C2= 2 • C1
Separate nFET and pFET unit transistors
Unit devices are not restricted to individual transistors
ENEE 359a
Lecture/s 9
Transistor Sizing
Sizing I: Complex Gates
Bruce Jacob
University of
Maryland
ECE Dept.
Critical transistors: those in series
VDD
SLIDE 23
A
B
2 nets in series:
scale each by 2x
C
D
•
•
•
UNIVERSITY OF MARYLAND
E
Two devices
in series: scale
each by 2x
OUT
N FETs in series => scale each by factor of N
Ignore FETs in parallel (assume worst case: only 1 on)
Ultimate goal: total resistance of net = 1 square
ENEE 359a
Lecture/s 9
Transistor Sizing
Sizing I: Complex Gates
Bruce Jacob
University of
Maryland
ECE Dept.
Critical transistors: those in series
VDD
SLIDE 24
A
2x1
2x1
B
2 nets in series:
scale each by 2x
•
•
•
UNIVERSITY OF MARYLAND
C
4x1
D
4x1
2x1
E
Two devices
in series: scale
each by 2x
OUT
N FETs in series => scale each by factor of N
Ignore FETs in parallel (assume worst case: only 1 on)
Ultimate goal: total resistance of net = 1 square
ENEE 359a
Lecture/s 9
Transistor Sizing
Examples
Bruce Jacob
VDD
University of
Maryland
ECE Dept.
SLIDE 25
A
B
C
E
D
OUT
A
B
UNIVERSITY OF MARYLAND
E
C
D
ENEE 359a
Lecture/s 9
Transistor Sizing
Examples
Bruce Jacob
VDD
University of
Maryland
ECE Dept.
SLIDE 26
A
C
D
2
VDD
2
4
B
2
OUT
UNIVERSITY OF MARYLAND
2
B
2
2
C
2
6
B
C
12 6
E
D
12
A
2
B
2
2
C
2
E
2
Assuming Wp = 3Wn
E
2
6
OUT
E
4
A
A
D
D
ENEE 359a
Lecture/s 9
Transistor Sizing
Examples
Bruce Jacob
VDD
A
University of
Maryland
ECE Dept.
B
C
SLIDE 27
D
B
C
OUT
A
D
B
A
UNIVERSITY OF MARYLAND
B
C
ENEE 359a
Lecture/s 9
Transistor Sizing
Examples
Bruce Jacob
VDD
A
University of
Maryland
ECE Dept.
6
SLIDE 28
6
B
18 6
D
B
18
C
18
6
C
OUT
2
D
A
UNIVERSITY OF MARYLAND
2
2
B
3
A
3
B
2 3
C
ENEE 359a
Lecture/s 9
Transistor Sizing
Ways to Improve Gate Delay
Bruce Jacob
tp ≈ (tpHL + tpLH) ≈ [CL ÷ (k’ W/L VDD)]
University of
Maryland
ECE Dept.
Reduce CL
SLIDE 29
•
•
internal diffusion capacitance of the gate itself
(keep the drain diffusion as small as possible)
other terms: interconnect capacitance & fanout
Increase W/L ratio of the transistor
•
•
the most powerful and effective performance
optimization tool in the hands of the designer
watch out for self-loading! – when the intrinsic
capacitance dominates the extrinsic load
Increase VDD
•
•
•
UNIVERSITY OF MARYLAND
can trade-off energy for performance
increasing VDD above a certain level yields only very
minimal improvements
reliability concerns enforce a firm upper bound on VDD
ENEE 359a
Lecture/s 9
Transistor Sizing
Gate Delay, Revisited
Bruce Jacob
VDD
University of
Maryland
ECE Dept.
VDD
Rp
CL
SLIDE 30
VOUT
VOUT
CL
CL
Rn
LH scenario
HL Scenario
tp ≈ (tpHL + tpLH) ≈ 0.7RrefCref (1 + Cext/SCiref)
•
•
UNIVERSITY OF MARYLAND
widening the PMOS improves tpLH (Rp is lower)
but degrades tpHL (increases intrinsic capacitance
GGD and GDB)
widening the NMOS improves tpHL (Rn is lower)
but degrades tpLH (increases intrinsic capacitance
GGD and GDB)
ENEE 359a
Lecture/s 9
Transistor Sizing
Gate Delay, Revisited
Bruce Jacob
University of
Maryland
ECE Dept.
So far have sized the PMOS and NMOS so
that the Req’s match (ratio between 2 & 3.5)
SLIDE 31
•
•
symmetrical VTC
equal high-to-low and low-to-high propagation delays
If speed is the only concern, reduce the
width of the PMOS device!
•
widening the PMOS degrades tpHL due to larger
parasitic capacitance (intrinsic capacitance)
B = (W/Lp)/(W/Ln)
•
•
UNIVERSITY OF MARYLAND
r = Reqp/Reqn (resistance ratio of identically-sized
PMOS and NMOS)
Bopt ≈ √r if wiring capacitance negligible
ENEE 359a
Lecture/s 9
Transistor Sizing
Gate Delay, Revisited
Bruce Jacob
5 x 10
University of
Maryland
ECE Dept.
tpLH
4.5
tp(sec)
SLIDE 32
-11
tpHL
tp
4
3.5
3
1
2
3
4
5
β = (W/Lp)/(W/Ln )
•
•
UNIVERSITY OF MARYLAND
Ω/13 kΩ
Ω) [what we’ve looked at]
ß of 2.4 (Rp/Rn = 31 kΩ
gives symmetric response
ß of 1.6 to 1.9 gives optimal performance
ENEE 359a
Lecture/s 9
Transistor Sizing
Bruce Jacob
University of
Maryland
ECE Dept.
Inverter Delay
tp = 0.7RrefCref (1 + Cext/SCiref)
C int = γ C g
SLIDE 33
tp
C ext

= t p0 1 + -----------

γ C g
f
t p = t p0  1 + --

γ
Propagation time is function of ratio of
external to internal capacitance
This ratio is called fan-out, f
Gamma term is function of technology, γ ≈ 1
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Sizing & Big Gates
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 34
Sizing for Large Capacitive Loads
Cin1
A3(Wp1/Wn1)
A1(Wp1/Wn1)
A0(Wp1/Wn1)
A2(Wp1/Wn1)
Cload
Supose Cload large (e.g. off-chip wires)
•
•
Scale each inverter (both FETs in the circuit) by a
factor A (input capacitances scale by A)
if input C to last inverter * A = Cload
(i.e., Cload looks like N+1th inverter) then we have:
Input C of last inverter = Cin1 AN = Cload
•
Rearranging:
A = [Cload ÷ Cin1]1/N
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Sizing & Big Gates
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 35
Sizing for Large Capacitive Loads
Cin1
A0(Wp1/Wn1)
•
•
•
A3(Wp1/Wn1)
A1(Wp1/Wn1)
A2(Wp1/Wn1)
Capacitances increase by factor of A left to right
Resistances decrease by factor of A left to right
Total delay (tpHL + tpLH):
(Rn1+Rp1) • (Cout1+ACin1) +
(Rn1+Rp1)/A • (ACout1+A2Cin1) + …
= N (Rn1+Rp1) • (Cout1+ACin1)
•
Find optimal chain length:
Nopt = ln(Cload ÷ Cin1)
UNIVERSITY OF MARYLAND
Cload
ENEE 359a
Lecture/s 9
Transistor Sizing
Sizing & Big Gates
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 36
I/O Pad: large structures are ESD diodes
and inverter chains (scale: pad is ~65 µm)
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Bruce Jacob
Example
2/1
University of
Maryland
ECE Dept.
SLIDE 37
Cin = 2.5fF
Cload = 20pF
Load is ~8000x that of single inverter’s
input capacitance: find optimal solution.
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Example
Bruce Jacob
.5/.25
1.4/.7
3.6/1.8
9.8/4.9
27/13
72/36
194/97
523/262 1412/706
University of
Maryland
ECE Dept.
SLIDE 38
(sizes in microns)
Cload = 20pF
Nopt = ln(20pF/2.5fF) = 8.98 => 9 stages
Scaling factor A = (20pF/2.5fF)1/9 = 2.7
Total delay = (tpHL + tpLH)
= N (Rn1+Rp1) • (Cout1+ACin1)
= N (Rn1+Rp1) • (Cout1 + [Cload ÷ Cin1]1/N Cin1)
(assume Cin1 = 1.5Cout1 = 2.5 fF)
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= 9 • (31/9 + 13/3) • (1.85fF + 2.7 • 2.5fF)
= 602 ps (0.6 ns)
ENEE 359a
Lecture/s 9
Transistor Sizing
Generalize: Logical Effort
Bruce Jacob
University of
Maryland
ECE Dept.
Want to find minimum delay for chains:
SLIDE 39
Cin
Cload
Main Points:
UNIVERSITY OF MARYLAND
•
Path length is (maybe) fixed; find scaling
•
Want constant scaling factor along path
[ this gives same gate effort at each stage ]
•
RC delay of a gate uses sum of internal C
(its own Cout) and input of next gate (Cin)
ENEE 359a
Lecture/s 9
Transistor Sizing
Definitions
Bruce Jacob
University of
Maryland
ECE Dept.
g = Gate-level logical effort
= ratio of its input capacitance
to that of INVERTER
SLIDE 40
A
r
r
2
B
2
g nand
UNIVERSITY OF MARYLAND
n+r
= ------------1+r
A
A
4r
B
4r
C
4r
D
4r
1B 1 1
g nor
C
1
D
1 + nr
= ---------------1+r
ENEE 359a
Lecture/s 9
Transistor Sizing
Definitions
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 41
Total Path Effort H = GFB
Optimal gate effort h =
N
H
G = Path Logical Effort
Cin
Cload
G path = g inv ⋅ g nand ⋅ g nand ⋅ g nor ⋅ g inv
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Definitions
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 42
Total Path Effort H = GFB
Optimal gate effort h =
N
H
F = Effective Fan-Out of Chain
Cin
Cload
C load
F = ------------C in
Also called Electrical Effort
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Definitions
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 43
Total Path Effort H = GFB
Optimal gate effort h =
N
H
B = Path Branching Effort
Cin
B =
∑ b node
b node
UNIVERSITY OF MARYLAND
Cload
C on-path + C off-path
= ---------------------------------------------C on-path
ENEE 359a
Lecture/s 9
Transistor Sizing
Definitions
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 44
Total Path Effort H = GFB
Optimal gate effort h =
N
H
Redefine inverter delay:
fg 
f

+
-----=
t
t
p
t p = t p0  1 + --
=>
p
p0



γ
γ
Total delay through path:
f i gi

D = t p0 ∑ p i + ----------

γ 
Minimum delay through path:
N H
N
D = t p0  ∑ p i + ----------------

γ 
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Definitions
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 45
Total Path Effort H = GFB
Optimal gate effort h =
N
H
Gate effort hi = gifi
Sizing si for gate i in chain:
i –1
g
s
f j
1 1


s i = ------------- ∏ ---- gi 
 b j
j =1
UNIVERSITY OF MARYLAND
ENEE 359a
Lecture/s 9
Transistor Sizing
Analysis
Bruce Jacob
University of
Maryland
ECE Dept.
Find minimum delay for chain (assume r=2):
4/3
4/3
SLIDE 46
Cin = 20fF
7/3
Cload = 500fF
G = (1)(4/3)(4/3)(7/3)(1) = 4.15
F = 500/20 = 25
B = 1 (no branching)
h =
UNIVERSITY OF MARYLAND
N
H =
5
103.75 = 2.53
ENEE 359a
Lecture/s 9
Transistor Sizing
Analysis
Bruce Jacob
University of
Maryland
ECE Dept.
Find minimum delay for chain (assume r=2):
4/3
SLIDE 47
Cin = 20fF
4/3
fi = h / gi
f1 = 2.53
f2 = 2.53 • 3/4 = 1.9
f3 = 2.53 • 3/4 = 1.9
f4 = 2.53 • 3/7 = 1.1
f5 = 2.53
s1 = 1
s2 = f1 • g1/g2 = 1.9
s3 = f1f2 • g1/g3 = 3.6
s4 = f1f2f3 • g1/g4 = 3.9
s5 = f1f2f3f4 • g1/g5 = 10.0
UNIVERSITY OF MARYLAND
7/3
Cload = 500fF