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Building D Flip Flops • Combinational Circuit Components – Switches – Voltage inverters • D Clocked Latch – Feedback to store bits • D Flip Flop – Two D clocked latches Galen Sasaki EE 260 University of Hawaii 1 Building D Flip Flops D Flip Flops D Clocked Latches Primitive Combinational Circuits (Switches/Transisters) Galen Sasaki EE 260 University of Hawaii 2 Combinational Circuit Components Normally Open Switch Control = L Control = H open closed L Normally Closed Switch closed L Galen Sasaki EE 260 University of Hawaii H open H 3 Combinational Circuit Components Voltage Inverters (2 symbols) Galen Sasaki EE 260 University of Hawaii Active Device L H H L 4 A Simple 1-Bit Memory D Q Input to load new state value Galen Sasaki EE 260 University of Hawaii State value (1 bit) 5 A Simple 1-Bit Memory D Q Input to load new state value State value (1 bit) Two configurations: Hold (store) = hold onto the state value Load = load a new state value Galen Sasaki EE 260 University of Hawaii 6 Holding (Storing) With Voltage Inverters Devices drive each other Galen Sasaki EE 260 University of Hawaii 7 Holding (Storing) With Voltage Inverters Devices drive each other H Galen Sasaki EE 260 University of Hawaii 8 Holding (Storing) With Voltage Inverters Devices drive each other H H L Galen Sasaki EE 260 University of Hawaii 9 Holding (Storing) With Voltage Inverters Devices drive each other H H L L Galen Sasaki EE 260 University of Hawaii 10 Holding (Storing) With Voltage Inverters Devices drive each other H H L L L L H H Galen Sasaki EE 260 University of Hawaii 11 Simple Memory: Two Configurations D Q Input to load new state value State value (1 bit) Two configurations: Hold (store) = hold onto the state value Load = load a new state value Galen Sasaki EE 260 University of Hawaii 12 Simple Memory: Two Configurations Hold D Load Q Galen Sasaki D EE 260 University of Hawaii Q 13 Simple Memory: Two Configurations Hold D Load Q D Switches Galen Sasaki Q Switches EE 260 University of Hawaii 14 D Clocked Latch clock Q D clock clock = L : Hold clock = H : Load Galen Sasaki EE 260 University of Hawaii 15 D Clocked Latch Hold D Q Clock Q =L Clock It similar to a D flip flop but it reacts to the clock differently Load Q=D D Q Clock = H It’s “transparent” Galen Sasaki EE 260 University of Hawaii 16 Comparing Flip Flop and Latch D Q Clock Clock D Q-FlipFlop Q-Latch Galen Sasaki EE 260 University of Hawaii 17 Comparing Flip Flop and Latch D Q Clock Clock D T1 T2 Q-FlipFlop T3 Q-Latch Galen Sasaki EE 260 University of Hawaii 18 Comparing Flip Flop and Latch D Q Clock Clock D Q-FlipFlop Q-Latch Galen Sasaki EE 260 University of Hawaii 19 Comparing Flip Flop and Latch D Q Clock Clock D Q-FlipFlop Q-Latch Store Galen Sasaki EE 260 University of Hawaii Store Store 20 D Flip Flop vs. D Clocked Latch • D flip flop – Triggered on positive edge of clock – Output Q (and state) changes only at a time instant • D clocked latch – Output Q changes (with D) while clock is H – Output Q changes during a window of time – Trickier to use since lots of changes can happen during a time duration • Flip flops are preferred to latches in designing circuits • Latches are used in memory circuits, e.g., RAM Galen Sasaki EE 260 University of Hawaii 21 D Flip Flop D Clock Galen Sasaki Q D Q Clock EE 260 University of Hawaii 22 D Flip Flop D Q Clock Clock = L Galen Sasaki Load D Q D Q Clock Hold EE 260 University of Hawaii 23 D Flip Flop D Q Clock D Q Clock Clock = L Load D Q Hold Clock = H Hold Load D Q Galen Sasaki EE 260 University of Hawaii 24 D Flip Flop Load (loads input) Hold (output doesn’t change) L D Clock Q D Q Clock Input really doesn’t get stored until the upward clock transition Clock Galen Sasaki EE 260 University of Hawaii 25 D Flip Flop Load (loads input) H Hold (output doesn’t change) L H D Clock Q D Q Clock Input really doesn’t get stored until the upward clock transition Clock Galen Sasaki EE 260 University of Hawaii 26 D Flip Flop Load (loads input) H Hold (output doesn’t change) Clock Q Hold D Clock H H L H D Load (transfers state to output) Q D Clock Q D Q Clock Input really doesn’t get stored until the upward clock transition Clock Galen Sasaki EE 260 University of Hawaii 27 Summary • Combinational circuit components – switches and voltage inverters • D clocked latch – Built from switches and voltage inverters – 2 configurations: load and hold • D flip flop – Built from two D latches in series Galen Sasaki EE 260 University of Hawaii 28
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