Download MOV Revisited.

Microprocessors
Monday, Apr. 6
Dr. Asmaa Farouk
Faculty of Engineering, Electrical Department,
Assiut University
Topics of Today
• Reading:
– Brey:
• Section 4.1:
MOV Revisited.
• Section 4.2:
PUSH / POP.
• Section 4.3:
Load Effective Address.
– Mazidi:
• Section 2.4:
Control Transfer Instructions.
• Section 3.0:
Arithmetic and Logic Instructions and Programs.
• Section 3.1:
Unsigned Addition and Subtraction.
Topics of Today
•
•
•
•
•
•
MOV Revisited.
PUSH / POP.
Load Effective Address.
Control Transfer Instructions.
Arithmetic and Logic Instructions and Programs.
Unsigned Addition and Subtraction.
MOV Revisited
• Machine Language:
– Is the native binary code that the microprocessor
understands and uses as its instructions to control
its operation.
– Instructions vary in length from 1 to 13 bytes.
– Over 100,000 variations of machine language
instructions.
• There is no complete list of these variations.
– Some bits in a machine language instruction are
given; remaining bits are determined for each
variation of the instruction.
MOV Revisited
• The Opcode:
– Selects the operation (addition, subtraction, etc.,)
performed by the microprocessor.
• Either 1 or 2 bytes long for most instructions.
– Figure (4-2) illustrates the first opcode byte (MSB) of
many instructions (not all of them).
Data are a byte or a word (W). If
W = 1, the data size is a word; if
Most 6 bits of the first byte are
W = 0, the
the binary opcode.
data size is always a byte.
MOV Revisited
• The Opcode:
– Selects the operation (addition, subtraction, etc.,)
performed by the microprocessor.
• Either 1 or 2 bytes long for most instructions.
– Figure (4-2) illustrates the general form of the first
opcode byte of many instructions (not all of them).
Direction (D) of the data flow. If D = 1, data flow to
the register REG field from the R/M field (in the
second byte of an instruction). If D = 0, data flow to
the R/M field from the REG field.
MOV Revisited
• The Opcode: (Cont.)
– Figure (4-3) illustrates the second opcode byte (LSB)
of many instructions.
MOV Revisited
• MOD Field:
– Specifies addressing mode and
Example: MOV AL, [DI]
Example: MOV AL, [DI + 1000H]
whether a displacement is
present with the selected type. Example: MOV AL, [DI + 2]
• If the MOD field contains a 00, 01,
or 10, the R/M field selects one of
the data memory addressing
modes.
MOV Revisited
• MOD Field: (Cont.)
– All 8-bit displacements are sign-extended into 16bit displacements when the processor executes the
instruction.
• If the 8-bit displacement is 00H –7FH (positive), it is signextended to 0000H – 007FH before adding to the offset
address.
• If the 8-bit displacement is 80H – FFH (negative), it is signextended to FF80H – FFFFH.
– Some assembler programs do not use the 8-bit
displacements and instead default to all 16-bit
displacements.
MOV Revisited
• Register Assigment:
– If MOD field contains
11, it selects the
register addressing
mode, using the R/M
field.
MOV Revisited
• Register Assignment: (Cont.)
– Example: suppose a 2-byte instruction, 8BECH,
appears in a machine language program, as
illustrated in Figure (4-4).
MOV Revisited
• Register Assignment: (Cont.)
– Example: suppose a 2-byte instruction, 8BECH,
appears in a machine language program, as
illustrated in Figure (4-4).
The opcode is 100010, a
MOV instruction.
MOV Revisited
• Register Assignment: (Cont.)
– Example: suppose a 2-byte instruction, 8BECH,
appears in a machine language program, as
illustrated in Figure (4-4).
D = 1, so data moves to the
destination register
specified in the REG field
and from R/M field.
MOV Revisited
• Register Assignment: (Cont.)
– Example: suppose a 2-byte instruction, 8BECH,
appears in a machine language program, as
illustrated in Figure (4-4).
REG = 101, indicating register
BP, so the MOV instruction
moves data to register BP.
MOV Revisited
• Register Assignment: (Cont.)
– Example: suppose a 2-byte instruction, 8BECH,
appears in a machine language program, as
illustrated in Figure (4-4).
W = 1, so a word is moved.
MOV Revisited
• Register Assignment: (Cont.)
– Example: suppose a 2-byte instruction, 8BECH,
appears in a machine language program, as
illustrated in Figure (4-4).
MOD = 11, register
addressing mode, specified
in R/M field.
MOV Revisited
• Register Assignment: (Cont.)
– Example: suppose a 2-byte instruction, 8BECH,
appears in a machine language program, as
illustrated in Figure (4-4).
R/M = 100 , SP register;
therefore, this instruction
moves data from SP to BP.
MOV Revisited
• Register Assignment: (Cont.)
– Example: suppose a 2-byte instruction, 8BECH,
appears in a machine language program, as
illustrated in Figure (4-4).
– This is written in symbolic form as a “MOV BP,SP”
instruction.
MOV Revisited
• R/M Memory Addressing:
– If the MOD field contains a 00, 01, or 10, the R/M
field takes on a new meaning.
– Figure (4-5) illustrates the machine language version
of the 16-bit instruction “MOV DL,[DI]” or
instruction 8AI5H.
Opcode 100010 (MOV),
D = 1 (to REG from
R/M), W = 0 (byte)
MOV Revisited
• R/M Memory Addressing:
– If the MOD field contains a 00, 01, or 10, the R/M
field takes on a new meaning.
– Figure (4-5) illustrates the machine language version
of the 16-bit instruction “MOV DL,[DI]” or
instruction 8AI5H.
MOD = 00 (no displacement).
MOV Revisited
• R/M Memory Addressing:
– If the MOD field contains a 00, 01, or 10, the R/M
field takes on a new meaning.
– Figure (4-5) illustrates the machine language version
of the 16-bit instruction “MOV DL,[DI]” or
instruction 8AI5H.
REG=010 (DL).
R/M=101 ([DI]).
MOV Revisited
• R/M Memory Addressing: (Cont.)
– If the instruction changes to “MOV DL, [DI+1]”, the
MOD field changes to 01 (8-bit displacement).
• First 1 byte of the instruction remains the same.
• Instruction now becomes 8A5501H instead of 8A15H.
• The 8-bit displacement appends to the first 2 bytes of
the instruction to form a 3-byte instruction instead of 2
bytes.
MOV Revisited
• Special Memory Addressing:
– Occurs when memory data are referenced by only
the displacement mode of addressing for 16-bit
instructions.
– Examples: “MOV [1000H],DL” and “MOV NUMB,DL”
instructions.
• First instruction moves contents of register DL into data
segment memory location 1000H.
• Second instruction moves register DL into symbolic data
segment memory location NUMB.
MOV Revisited
• Special Memory Addressing: (Cont.)
– When an instruction has only a displacement, MOD
field is always 00; R/M field is always 110.
– The assembler uses an 8-bit displacement when
[BP] is referenced in an instruction.
MOV Revisited
• Special Memory Addressing: (Cont.)
Machine code for the instruction
MOV [1000H],DL. A 4-byte
instruction.
MOV Revisited
• Special Memory Addressing: (Cont.)
Machine code for the instruction
MOV [BP],DL .
A 3-byte instruction with a
displacement of 00H.
There is no MOD = 00 with BP
register addressing.
MOV Revisited
• An Immediate Instruction:
– Example: MOV WORD PTR [BX+1000H] ,1234H
• Moves a 1234H into a word-sized memory location
addressed by sum of 1000H, BX, and DS x 10H (shifted
DS).
• WORD PTR directive, indicating size of 2 bytes.
• Likewise, BYTE PTR and DWORD PTR indicating sizes of 1
and 4 bytes, respectively.
– 6-byte instruction.
• 2 bytes for the opcode; 2 bytes are the data of 1234H; 2
bytes are the displacement of 1000H.
MOV Revisited
• An Immediate Instruction: (Cont.)
Note: the opcode for MOV
(immediate addressing) is
different than the previous
MOV (100010).
MOV Revisited
• Segment MOV Instructions:
– If the contents of a segment register are moved by
MOV, PUSH, or POP instructions, a special bits (REG
field) select the segment register.
MOV Revisited
• Segment MOV Instructions:
– The opcode for this type of MOV instruction is
different for the prior MOV instructions.
• An immediate segment register MOV is not available in
the instruction set.
– To load a segment register with immediate data, first
load another register with the data and move it to a
segment register.
– Segment registers can be moved between any 16-bit
register or 16-bit memory location.
• Example: MOV [DI],DS stores the contents of DS into the
memory location addressed by DI in the data segment.
MOV Revisited
• Segment MOV Instructions: (Cont.)
– Figure 4–10 shows a MOV BX,CS instruction
converted to binary code.
Topics of Today
•
•
•
•
•
•
MOV Revisited.
PUSH / POP.
Load Effective Address.
Control Transfer Instructions.
Arithmetic and Logic Instructions and Programs.
Unsigned Addition and Subtraction.
PUSH / POP
• Important instructions that store and retrieve
data from the LIFO (last-in, first-out) stack
memory.
• Six forms of the PUSH and POP instructions:
– Register, memory, segment register, flags,
immediate, all registers.
– PUSH and POP immediate and all registers are not
available in 8086/8088 microprocessors.
PUSH / POP
• Register addressing allows contents of any 16bit register to transfer to & from the stack (32
bit registers allowed in 80386 and above).
• Memory addressing PUSH and POP instructions
store contents of a 16- or 32 bit (allowed in
80386 and above) memory location on the
stack or stack data into a memory location.
• Immediate addressing allows immediate data to
be pushed onto the stack, but not popped off
the stack.
PUSH / POP
• Segment register addressing allows contents of
any segment register to be pushed onto the
stack or removed from the stack.
– ES may be pushed, but data from the stack may
never be popped into ES.
• The flags may be pushed or popped from the
stack.
• Contents of all registers may be pushed or
popped.
PUSH / POP
• PUSH:
– Transfers 2 bytes of data to the stack.
• 80386 and above transfer 2 or 4 bytes.
– PUSHF instruction (push flags) copies the contents
of the flag register to the stack.
– PUSHA instruction (push all) copies contents of the
internal register set, except the segment registers,
to the stack.
• Requires 16 bytes of stack memory space to store eight
16-bit registers.
PUSH / POP
• PUSH: (Cont.)
– PUSHA copies the registers to the stack in the
following order:
AX, CX, DX, BX, SP, BP, SI, and DI.
– After all registers are pushed, the content of the SP
register is decremented by 16.
PUSH / POP
• PUSH: (Cont.)
– PUSHAD and POPAD instructions push and pop the
contents of the 32-bit register set in 80386 and
above.
• Requires 32 bytes of stack storage space.
PUSH / POP
• PUSH: (Cont.)
PUSH / POP
• POP:
– Performs the inverse operation of PUSH.
– POP removes data from the stack and places it in a
target 16-bit register, segment register, or a 16-bit
memory location.
• Not available as an immediate POP.
– POPF instruction (pop flags) removes a 16-bit
number from the stack and places it in the flag
register.
• POPFD removes a 32-bit number from the stack and
places it into the extended flag register (in 80386 and
above).
PUSH / POP
• POP: (Cont.)
– POPA instruction (pop all) removes 16 bytes of data
from the stack and places them into the following
registers, in the order shown: DI, SI, BP, SP, BX, DX,
CX, and AX.
• Reverse order from placement on the stack by PUSHA
instruction, causing the same data to return to the same
registers.
– POP CS is not allowed.
PUSH / POP
• POP: (Cont.)
PUSH / POP
• Initializing the Stack:
– When the stack area is initialized, load both the
stack segment (SS) register and the stack pointer
(SP) register.
– The .STACK statement in assembly initializes both SS
and SP.
– If the stack is not specified in the program, a
warning will appear when the program is linked.
– This error often causes the computer program to
crash.
Topics of Today
•
•
•
•
•
•
MOV Revisited.
PUSH / POP.
Load Effective Address.
Control Transfer Instructions.
Arithmetic and Logic Instructions and Programs.
Unsigned Addition and Subtraction.
Load Effective Address
• LEA:
– Loads a 16- or 32-bit register with the offset
address of the data specified by the operand.
– Example: LEA AX, NUMB, loads AX with the offset
address of NUMB.
Load Effective Address
• LEA: (Cont.)
– What is the difference between OFFSET directive
and LEA instruction?
• OFFSET performs same function as LEA instruction if the
operand is a displacement.
Example: LEA AX, NUMB
&
MOV AX, OFFSET NUMB have the same result.
• LEA and MOV with OFFSET instructions are both the same
length (3 bytes).
Load Effective Address
• LEA: (Cont.)
– What is the difference between OFFSET directive
and LEA instruction?
• OFFSET is more efficient than LEA instruction, for simple
operands such as NUMB.
– It takes the microprocessor longer to execute the LEA.
• If the operand is an array, OFFSET cannot be used.
– OFFSET is not used for operands such as LIST [DI] or [DI].
Load Effective Address
• LDS and LES load any 16-bit register with an
offset address retrieved from a memory
location, then load either DS or ES with a
segment address retrieved from memory.
• In 80386 and above, LFS, LGS, and LSS are
added to the instruction set.
• Example: LDS BX,[DI]
– Transfers the 32-bit number (4 bytes), addressed by
DI (in the data segment), into the BX and DS
registers.
• The offset address first, followed by the segment address.
Topics of Today
•
•
•
•
•
•
MOV Revisited.
PUSH / POP.
Load Effective Address.
Control Transfer Instructions.
Arithmetic and Logic Instructions and Programs.
Unsigned Addition and Subtraction.
Control Transfer Instructions
• FAR and NEAR:
– In the sequence of instructions, it is often necessary
to transfer program control to a different location.
• If control is transferred to a memory location within the
current code segment, it is NEAR.
– Sometimes called “intrasegment” (within segment).
• If control is transferred outside the current code
segment, it is a FAR jump.
– Or “intersegment “(between segments).
Control Transfer Instructions
• FAR and NEAR: (Cont.)
– As the CS:IP registers always point to the address of
the next instruction to be executed, they must be
updated when a control transfer is executed.
• In a NEAR jump, the IP is updated and CS remains the
same, since control is still inside the current code
segment.
• In a FAR jump, because control is passing outside the
current code segment, both CS and IP have to be
updated to the new values.
Control Transfer Instructions
• Conditional Jumps:
– Conditional jumps have mnemonics such as JNZ
(jump if not zero) and JC (jump if carry).
– In the conditional jump, control is transferred to a
new location if a certain condition is met.
• The flag register indicates the current condition.
– For example, with "JNZ label", the processor looks at the zero
flag to see if it is raised.
– If not, the CPU starts to fetch and execute
instructions from the address of the label.
• If ZF = 1, it will not jump but will execute the next
instruction below the JNZ.
Control Transfer Instructions
• Conditional Jumps: (Cont.)
Control Transfer Instructions
• Short Jumps:
– All conditional jumps are short jumps.
• The address of the target must be within -128 to +127
bytes of the IP.
– The conditional jump is a two-byte instruction.
• One byte is the opcode of the J condition.
• The second byte is a value between 00 and FFH.
– An offset range of 00 to FF gives 256 possible addresses (spited
between backward jump -128 and forward jump +127).
– In a backward jump, the second byte is the 2's
complement of the displacement value.
• Second byte added to the IP of the instruction after jump.
Control Transfer Instructions
• Short Jumps: (Cont.)
– Example:
IP
Opcode
Instructions
Original code
• "JNZ AGAIN" was assembled as "JNZ 000D", and 000D is
the address of the instruction with the label AGAIN.
• "JNZ 000D" has the opcode 75 and the target address FA.
Control Transfer Instructions
• Short Jumps: (Cont.)
– Example:
IP
Opcode
Instructions
Original code
• The address of the next instruction (MOV,SUM, AL) is
0013. It is added to FA to calculate the address of label
AGAIN (carry is dropped, 0013 + FA = 000D).
Control Transfer Instructions
• Short Jumps: (Cont.)
– Example:
IP
Opcode
Instructions
Original code
• FA is the 2's complement of -6, meaning that the address
of the target is -6 bytes of the IP of the next instruction.
Control Transfer Instructions
• Short Jumps: (Cont.)
– A forward jump target address is calculated
similarly, with a positive displacement.
• Example:
• "JB NEXT" has the opcode 72, a displacement of 06 and
next instruction address is 000C.
• The target address is (000CH + 0006H) giving IP = 0012 for
the NEXT label.
Control Transfer Instructions
• Short Jumps: (Cont.)
– A forward jump target address is calculated
similarly, with a positive displacement.
• Example:
• "JA NEXT" has the opcode 72, a displacement of 02 and
next instruction address is 0010.
• The target address is (0010H + 0002H) giving IP = 0012 for
the NEXT label.
Control Transfer Instructions
• Short Jumps: (Cont.)
– For conditional jumps, the address of the target
address can never be more than -128 to +127 bytes
away from the IP associated with the instruction
following the jump.
• Any attempt is made to violate this rule will generate a
"relative jump out of range" message.
Control Transfer Instructions
• Unconditional Jumps:
– Transfers control to the target location label
unconditionally, in the following forms:
1. SHORT JUMP: in the format "JMP SHORT label".
– A jump within -128 to +127 bytes of memory relative to the
address of the current IP, opcode EB.
Control Transfer Instructions
• Unconditional Jumps:
– Transfers control to the target location label
unconditionally, in the following forms:
2. NEAR JUMP: the default, has the format "JMP label".
– A jump within the current code segment, opcode E9.
a) Direct JUMP: exactly like the short jump.
» Except that the target address can be anywhere in the
segment in the range +32767 to -32768 of the current IP.
b) Register indirect JUMP: target address is in a register.
» In "JMP BX", IP takes the value BX.
c) Memory indirect JUMP: target address is the contents of two
memory locations, pointed at by the register.
» "JMP [DI]" will replace the IP with the contents of memory
locations pointed at by DI and DI+1.
Control Transfer Instructions
• Unconditional Jumps: (Cont.)
– Transfers control to the target location label
unconditionally, in the following forms:
3. FAR JUMP: in the format "JMP FAR PTR label“.
– A jump out of the current code segment.
– IP and CS are both replaced with new values.
Control Transfer Instructions
• CALL Statements:
– The CALL instruction is used to call a procedure, to
perform tasks that need to be performed frequently.
– The target address could be in the current segment,
in which case it will be a NEAR call or outside the
current CS segment, which is a FAR call.
– The microprocessor saves the address of the
instruction following the call on the stack.
• To know where to return, after executing the subroutine.
• In the NEAR call only the IP is saved on the stack.
• In a FAR call both CS and IP are saved.
Control Transfer Instructions
• CALL Statements: (Cont.)
– For control to be transferred back to the caller, the
last subroutine instruction must be RET (return).
• For NEAR calls, the IP is restored.
• For FAR calls, CS & IP are restored.
– Example:
• From the IP numbers, this is a NEAR call.
– Only IP is saved on the stack.
• Assume SP = FFFEH:
– IP address 0206, (instruction after CALL) is saved.
Control Transfer Instructions
• CALL Statements: (Cont.)
– Last instruction of the called subroutine must be a
RET, that directs the CPU to POP the top 2 bytes of
the stack into the IP and resume executing at offset
address.
Control Transfer Instructions
• Rules for Names in Assembly Language:
– The names used for labels consist of:
• Alphabetic letters in both upper- and lowercase.
• The digits 0 through 9.
• Question mark (?), Period (.), At (@), Underline (_) and
Dollar sign ($).
– Each label name must be unique.
• They may be up to 31 characters long.
– The first character must be an alphabetic or special
character.
• It cannot be a digit.
Topics of Today
•
•
•
•
•
•
MOV Revisited.
PUSH / POP.
Load Effective Address.
Control Transfer Instructions.
Arithmetic and Logic Instructions and Programs.
Unsigned Addition and Subtraction.
Arithmetic and Logic Instructions and Programs
• In this chapter we will be enable to:
– Demonstrate how 8-bit and 16-bit unsigned
numbers are added in the x86.
– Convert data to any of the forms:
• ASCII, packed BCD, unpacked BCD.
– Explain the effect of unsigned arithmetic
instructions on the flags.
Arithmetic and Logic Instructions and Programs
• In this chapter we will be enable to:
– Code the following Assembly language unsigned
arithmetic instructions:
• Addition instructions: ADD and ADC.
• Subtraction instructions SUB and SBB.
• Multiplication and division instructions MUL and DIV.
– Code BCD arithmetic instructions:
• DAA and DAS.
Arithmetic and Logic Instructions and Programs
• In this chapter we will be enable to:
– Code the Assembly language logic instructions:
• AND, OR, and XOR.
• Logical shift instructions SHR and SHL.
• The compare instruction CMP.
– Code bitwise rotation instructions
• ROR, ROL, RCR, and RCL.
– Demonstrate an ability to use all of the above
instructions in Assembly language programs.
Topics of Today
•
•
•
•
•
•
Control Transfer Instructions.
Arithmetic and Logic Instructions and Programs.
Unsigned Addition and Subtraction.
Unsigned Multiplication and Division.
Logic Instructions.
Rotate Instructions.
Unsigned Addition and Subtraction
• Unsigned numbers are data in which all the bits
are used to represent data.
– No bits are used for the positive or negative sign.
• Between 00 and FFH (0 to 255 decimal) for 8-bit data.
• Between 0000 and FFFFH (0 to 65535 decimal) for 16-bit
data.
– Applies to the ADD and SUB instructions.
Unsigned Addition and Subtraction
• Addition of Unsigned Numbers:
– ADD instruction:
– ADD and ADC are used to add two operands.
• The destination operand can be a register or in memory.
• The source operand can be a register, memory, or
immediate.
– Memory-to-memory operations are never allowed in x86
Assembly language.
• The instruction could change ZF, SF, AF, CF, or PF bits of
the flag register.
Unsigned Addition and Subtraction
• Case1: Addition of Individual Byte / Word Data:
– Program 3-1a uses AH to accumulate carries as the
operands are added to AL.
Unsigned Addition and Subtraction
• Case1: Addition of Individual Byte / Word Data:
EQU directive, assigns a label a
constant value.
Decimal nmbers are converted
to hex by the assembler:
125=7DH, 235=0EBH,
197=0C5H, 91=5BH, 48=30H.
Unsigned Addition and Subtraction
• Case1: Addition of Individual Byte / Word Data:
Three iterations of the loop:
1. In the first, 7DH is added to
AL: AH = 00.
CF = 0.
CX = 04.
ZF = 0.
Unsigned Addition and Subtraction
• Case1: Addition of Individual Byte / Word Data:
Three iterations of the loop:
2. Second, EBH is added to AL &
since a carry occurred, AH is
incremented: AL = 68H.
CF = 1.
CX = 03.
ZF = 0.
Unsigned Addition and Subtraction
• Case1: Addition of Individual Byte / Word Data:
Three iterations of the loop:
3. Third, C5H is added to AL,
again a carry increments AH:
AL = 2DH.
CX = 02.
ZF = 0.
Unsigned Addition and Subtraction
• Case1: Addition of Individual Byte / Word Data:
This process continues until CX
= 00 and the zero flag becomes
1, causing JNZ to fall through.
Unsigned Addition and Subtraction
• Case1: Addition of Individual Byte / Word Data:
The result will be saved
in the word-sized
memory set aside in the
data segment.
Unsigned Addition and Subtraction
• Case1: Addition of Individual Byte / Word Data:
– Due to pipelining it is strongly recommended that
the following lines of the program be replaced:
– The "ADC AH,00" instruction means: add 00+AH+CF
and place the result in AH.
• More efficient since the instruction "JNC OVER" has to
empty the queue of pipelined instructions and fetch the
instructions from the OVER target every time the carry is
zero (CF = 0).
Unsigned Addition and Subtraction
• Case2: Addition of Multiword Numbers:
– Assume a program to add large numbers.
• Numbers could be 8 bytes wide or more.
– The programmer must write the code to break the
large numbers into smaller chunks to be processed.
• Because the registers are 16 or 8 bits wide.
• A 16-bit register & an 8 byte operand wide would take a
total of four iterations.
• An 8-bit register with the same operands would require
eight iterations.
Unsigned Addition and Subtraction
• Case2: Addition of Multiword Numbers:
– In writing program 3-2, the first decision was the
directive for coding the data in the data segment.
DQ directive (Define
Quadword) can
represent data as large as
8 bytes wide.
Unsigned Addition and Subtraction
• Case2: Addition of Multiword numbers:
Before executing ADC, the carry
flag is cleared (CF = 0) using the
CLC (clear carry) instruction.
CX = 4, we need 4 iterations
(8 byte operands in 2 byte
registers).
Unsigned Addition and Subtraction
• Case2: Addition of Multiword numbers:
Three pointers have been used:
– SI for DATA1; DI for DATA2.
– BX for DATA3. (where the
result is saved).
Unsigned Addition and Subtraction
• Case2: Addition of Multiword numbers:
The ADC instruction is always
used, as the carry must be
added to the next-higher byte
(or word) in the next iteration.
Unsigned Addition and Subtraction
• Case2: Addition of Multiword numbers:
A new instruction, "LOOP XXXX",
replaces "DEC CX" and "JNZ XXXX".
– When "LOOP xxxx" is executed,
CX decrements Automatically:
• If CX is not 0, the processor will
jump to target address xxxx.
• If CX is 0, the next instruction
(below "LOOP xxxx") is executed.
Unsigned Addition and Subtraction
• Subtraction of Unsigned Numbers:
– In subtraction, x86 processors use 2's complement.
• Internal adder circuitry performs the subtraction
command.
– Main steps in executing the SUB instruction:
1. Take the 2's complement of the source operand.
2. Add it to the destination operand.
3. Invert the carry.
Unsigned Addition and Subtraction
• Subtraction of Unsigned Numbers: (Cont.)
– After execution:
• If CF = 0, the result is positive.
• If CF = 1, the result is negative and the destination has
the 2's complement of the result.
– Compute the 2's complement of the result to get the correct
negative number.
Unsigned Addition and Subtraction
• Subtraction of Unsigned Numbers: (Cont.)
– Example:
Unsigned Addition and Subtraction
• Subtraction of Unsigned Numbers: (Cont.)
NOT performs the 1's
complement of the operand.
The operand is incremented
to get the 2's complement.
Unsigned Addition and Subtraction
• SBB (Subtract with Borrow):
– SBB is used for multi-byte (multiword) numbers.
• It will take care of the borrow of the lower operand.
– If CF = 0, SBB works like SUB.
– If CF = 1, SBB subtracts 1 from the result.
Unsigned Addition and Subtraction
• SBB (Subtract with Borrow):
– Example:
PTR (pointer) directive is used
to specify the size of the
operand when it differs from
DD directive (Define
the defined size.
Double word) can
represent data as large as
"WORD PTR" tells the assembler
4 bytes wide.
to use a word operand, though
the data is defined as a double
word.
Questions?