Download CMOS Inverter

EE4271
VLSI Design
Dr. Shiyan Hu
Office: EERC 731
[email protected]
The Inverter
Adapted and modified from Digital Integrated Circuits: A Design Perspective
by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.
© Digital Integrated Circuits2nd
Inverter
Circuit Symbols
© Digital Integrated Circuits2nd
Inverter
The CMOS Inverter: A First Glance
V DD
S
Vin=Vdd,Vout=0
Vin=0,Vout=Vdd
D
V in
V out
D
CL
S
© Digital Integrated Circuits2nd
Inverter
CMOS Inverter - First-Order DC Analysis
V DD
V DD
Rp
V out
V out
Rn
V in
V DD
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V in
0
Inverter
CMOS Inverter: Transient Response
V DD
V DD
Delay=0.69RC
Rp
V out
V out
CL
CL
Rn
V in
0
(a) Low-to-high
© Digital Integrated Circuits2nd
V in
V DD
(b) High-to-low
Inverter
For NMOS
NMOS In Inverter
VDD
1.
Vin=0, Vgsn=0<Vtn, Vdsn=Vout=Vdd, NMOS is
in cut-off region, X1.
2.
PMOS is on. Vout=Vdd.
3.
Vin=Vdd, instantaneously,
Vgsn=Vdd>Vtn,Vdsn=Vout=Vdd, VgsnVtn=Vdd-Vtn<Vdd, NMOS is in saturation
region, X2
4.
Instantaneously, Vgsp=0>Vtp. PMOS cut-off
5.
NMOS is on so Vdsn->0. The operating point
follows the arrow to the origin. Vout=0 at X3.
S
Vin
D
D
Vout
CL
S
© Digital Integrated Circuits2nd
Inverter
The CMOS Inverter
We enforce that
Idsp=-Idsn when
both transistors
are on for DC
analysis.
Assume that
Vtn=|Vtp|
V DD
S
D
V in
V out
D
CL
S
© Digital Integrated Circuits2nd
Inverter
The CMOS Inverter – 2
(Region A)
V DD
0<Vin<Vtn
|Vgsp|=|Vin-Vdd|>|Vtp|,
S |Vdsp|=|Vd-Vdd|~0<|VgspVtp| PMOS linear region
D
V in
V out
D
S
© Digital Integrated Circuits2nd
CL
Vd is close to
Vdd
Vgsn=Vin<Vtn,
NMOS cut-off
Inverter
The CMOS Inverter – 3
(Region B)
Vtn<Vin<Vdd/2
V DD
S
|Vgsp|=|Vin-Vdd|>Vdd/2>|Vtp|,
|Vdsp|~0<|Vgsp-Vtp|
PMOS linear region
D
V in
V out
D
S
© Digital Integrated Circuits2nd
CL
Vgsn=Vin>Vtn,
Vdsn=Vout=Vdd>Vgsn-Vtn
NMOS saturation region
Inverter
The CMOS Inverter - 4
© Digital Integrated Circuits2nd
Inverter
The CMOS Inverter – 5
(Region C)
Vin=Vout
V DD
Vgsn=Vdsn
Vgsp=Vdsp
S
|Vgsp|=|Vin-Vdd|>|Vtp|,
|Vdsp|>|Vgsp-Vtp|, saturation
D
V in
V out
D
S
© Digital Integrated Circuits2nd
CL
Vgsn>Vtn,
Vdsn>Vgsn-Vtn, saturation
Inverter
The CMOS Inverter - 6
Usually,
Usually we set
for equal rising and
falling propagation delay (same R for both
devices)
Since
© Digital Integrated Circuits2nd
, we have
Inverter
The CMOS Inverter 7
 Vin=Vout=Vdd/2
 The
above analysis is actually correct
for Vin=vdd/2 and all Vout such that
both devices are in saturation regions
 For NMOS, Vout>Vin-Vtn
 For PMOS, Vgsp-Vtp>Vdsp ->Vout<Vin-Vtp
 Vin-Vtn<Vout<Vin-Vtp,
so for
Vin=Vdd/2, Vout can vary around Vdd/2
© Digital Integrated Circuits2nd
Inverter
The CMOS Inverter – 9
(Region D)
V DD
Vdd/2<Vin<Vdd|Vtp|
|Vgsp|=|Vin-Vdd|>|Vtp|,
S |Vdsp|=|Vd-Vdd|>|VgspVtp|, PMOS saturation
region
D
V in
V out
D
S
© Digital Integrated Circuits2nd
Vout < Vdd/2
CL
Vgsn=Vin>Vtn,
Vdsn=Vout<Vgsn-Vtn
NMOS linear region
Inverter
The CMOS Inverter - 10
© Digital Integrated Circuits2nd
Inverter
The CMOS Inverter – 11
(Region E)
V DD
Vin>Vdd-|Vtp|
|Vgsp|=|Vin-Vdd|<|Vtp|,
S PMOS cut-off
D
V in
V out
D
S
© Digital Integrated Circuits2nd
CL
Vgsn=Vin>Vtn,
Vdsn<Vgsn-Vtn
NMOS linear
Inverter
The CMOS Inverter -12
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Inverter
The CMOS Inverter
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Inverter
Circuit Under Design
VDD
VDD
M2
M4
Vout
Vin
M1
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Vout2
M3
Inverter
Its Layout View
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Inverter