Download CMOS BUFFER DESIGN PROJECT

CMOS BUFFER DESIGN PROJECT
EE 307 W02
Dr. Braun
Jimmy Duong:
Benny Liu:
Christion Richert:
Derek West
[email protected]
[email protected]
[email protected]
[email protected]
http://www.calpoly.edu/~crichert/ee307/01_04.html
Due: 03/08/2002
Schematic:
Input Deck:
* CMOS Buffer Design Project
* EE 307 - Braun
* Group 4
* Vin is Node 2
Vin 2 0
Vcc 1 0
RB 1 3
Q1 4 3 2
R1 1 5
Q2 5 4 6
R2 6 0
RC 1 7
Q4 7 5 8
DTTL 8 11
Q3 11 6 0
RB11 11 1
PULSE(.1 3.8 0S .1nS .1nS 33nS 66nS)
5.0V
4.0K
MULTIE ; Q1 Input 1
1.6K
NPNT
1.0K
130
NPNT
SW
NPNT
5k
* CMOS load begins at node 11
* Vout is Node 30
Vdd 10 0
5.0V
R11 11 1
1k
L1 11 12
10nH
D1 12 10
CLAMP
D2 0 12
CLAMP
C1 12 0
20pF
MP 20 12 10 10 CMOSP (W=1u L=1u)
MN 20 12 0 0 CMOSN (W=1u L=1u)
*YOUR BUFFER GOES HERE
VBD1 26 0
5.0V
VBD2 29 0
MP1
MN1
MP2
MN2
5V
22 20 26 26 CMOSP (W=200u L=1u)
22 20 0 0 CMOSN (W=375u L=1u)
30 22 29 29 CMOSP (W=8900u L=1u)
30 22 0 0 CMOSN (W=8000u L=1u)
CLOAD 30 0
1nF
.MODEL MULTIE NPN (IS=2E-6 BF=100 BR=0.5
+ TF=1E-10 TR=1E-8 CJE=0.5P CJC=0.5P RC=5)
.MODEL NPNT NPN (TF=1E-10 TR=1E-8 CJE=0.5P
+ CJC=0.5P RC=5)
.MODEL SW D(IS=1E-14 TT=1E-10 RS=10 CJO=2P
+ VJ=0.7)
.MODEL CLAMP D(IS=1E-14 TT=1E-11 RS=10 CJO=2P VJ=0.7)
.MODEL CMOSN NMOS (LEVEL=3 PHI=0.600 TOX=1.78E-08 XJ=0.200U TPG=1
+ VTO=0.7623 DELTA=7.6940E-01 LD=1.1890E-07 KP=1.2379E-04
+ UO=638.1 THETA=1.2160E-01 RSH=6.5980E+00 GAMMA=0.5942
+ NSUB=4.0030E+16 NFS=7.0730E+12 VMAX=1.9160E+05 ETA=4.3410E-02
+ KAPPA=1.0510E-01 CGDO=3.4599E-10 CGSO=3.4599E-10
+ CGBO=4.1520E-10 CJ=2.6473E-04 MJ=0.9561 CJSW=4.0556E-10
+ MJSW=0.270227 PB=0.800 )
.MODEL CMOSP PMOS (LEVEL=3 PHI=0.600 TOX=1.78E-08 XJ=0.200U TPG=-1
+ VTO=-0.8814 DELTA=1.2220E+00 LD=4.5410E-08 KP=3.6685E-05
+ UO=189.1 THETA=1.7250E-01 RSH=5.5000E-01 GAMMA=0.4652
+ NSUB=2.4540E+16 NFS=7.7440E+12 VMAX=3.7770E+05 ETA=8.1730E-02
+ KAPPA=9.9830E+00 CGDO=1.3214E-10 CGSO=1.3214E-10
+ CGBO=4.2612E-10 CJ=5.5813E-04 MJ=0.4968 CJSW=2.0919E-10
+ MJSW=0.463227 PB=0.850)
.TRAN 1pS 1uS
.PRINT TRAN V(30)
.PLOT TRAN V(30)
.PROBE
.END
Calculations:
Finding the delay, power and area:
Area
The area of the buffer is found by add up the W*L values of our buffer.
Area = Wn1 *Ln1 + Wn2 *Ln2+ Wp1 *Lp1+ Wp2 *Lp2
Area = 375 u in * 1u in + 8000 u in * 1 u in + 200 u in * 1 u in + 8900 u in * 1 u in
Area = 17475 u in^2
Delay time
The delay time can be found by using the cursor to find tphl and tplh of V(30).
Delay time = (tphl + tplh) / 2
Delay time = (21.4 n s + 21.4 n s) / 2
Delay time = 21.4 n s
From the graph we can uses simple calculation to determine tplh and tphl times of the input and output voltage. To
find the tplh time we can take 50 percent of the high voltage for the output from low to high minus the 50 percent of
the high voltage for the input from low to high and divide by two. To find the tphl time we can take 50 percent of
the high voltage for the output from high to low minus the 50 percent of the high voltage for the input from high to
low and divide by two.
From the graph we can uses simple calculation to determine rise time and fall time of the input and output voltage.
To find the rise time we can take 10 percent of the high voltage for the output from low to high plus the 90 percent
of the high voltage for the input from low to high and divide by two. To find the fall time we can take 10 percent of
the high voltage for the output from high to low plus the 90 percent of the high voltage for the input from high to
low and divide by two.
Power Calculations
The power of the circuit can be found by using Pspice trace of the power. By looking at the graph of the average
power of (Vcc + Vdd + VBd1 + VBd2), we can see that the power of the circuit approaches 0.67 Watt.
frequency (GHz) delay (ns) power (W) area (u in^2) falltime (ns) risetime (ns) FOM (ns*W*u*in^2 / GHz)
0.015
21.4
0.67
17475
3.79
4.98
16703770
Voltage at Node 11:
Max and Min Voltages:
Rise time:
Fall time:
Propagation delay (tp):
Average Power:
Works Cited:
Braun, D. Supplemental Material. San Luis Obispo: Second Edition Copy Center, 2002.
Gopalan, K. Introduction To Digital Microelectronic Circuits. Chicago: McGraw-Hill, 1996.
http://www.ee.calpoly.edu/~dbraun/courses/ee307/W02/Project.html