Download PIN NAME

ALICE1_LHCB pinout
ANALOG
K.Wyllie 9/2/2000
M.Campbell 14/2/00
K.Wyllie 16/2/2000
PIN NAME
DIRECTION TYPE
DESCRIPTION
sub
wella
vssa
vdda
input
input
input
input
power
power
power
power
substrate connection (0V)
analog well connection (1.6V)
analog vss (0V)
analog vdd (1.6V)
sub_FE
input
power
‘quiet’ substrate for analog circuitry
GTL_REFa
input
bias
DAC_sense_I
DAC_sense_V
DAC_REF_VDD
DAC_REF_MID
analog_test_hi
analog_test_lo
output
output
input
input
input
input
analog
analog
bias
bias
analog
analog
GTL reference voltage (~800mV) for
analog ip pads
Current output of selected DAC
Voltage output of selected DAC
DAC reference voltage (1.6V)
DAC reference voltage (~800mV)
Test pulse amplitude hi (range vdd/2 – vdd)
Test pulse amplitude lo (range vdd/2 – vdd)
JTAG
TRESET*
input
digital
TDI0
input
digital
TDO
output
digital
TDI1
input
digital
TCLK
input
digital
TMS
input
digital
NB JTAG signals are POSITIVE ‘GTL’ logic:
Logic 1 is 1.2V
Logic 0 is 400mV
This assumes a GTL reference voltage of 800mV.
The exception is TRESET*, which is inverted.
jtag reset
jtag input 0
jtag output
jtag input 1
jtag clock
jtag mode select
DIGITAL
PIN NAME
DIRECTION TYPE
DESCRIPTION
well
sub
vdd
vss
input
input
input
input
power
power
power
power
Digital well connection (1.6V)
Digital substrate connection (0V)
Digital vdd (1.6V)
Digital vss (0V)
vdd_buff
vss_buff
well_buff
sub_buff
input
input
input
input
power
power
power
power
vdd for output data buffers (1.6V)
vss for output data buffers (0V)
well connection for buffer (1.6V)
sub connection for buffers vss (0V)
DATA*<0:31>
output
digital GTL
Data output
CLK
CLK*
NEVR*
STROBE*
CE*
ABORT*
DATA_RESET*
SHIFT_RESET*
TEST_PULSE*
ALICE
input
input
input
input
input
input
input
input
input
input
digital GTL
digital GTL
digital GTL
digital GTL
digital GTL
digital GTL
digital GTL
digital GTL
digital GTL
digital
System clock
System clock inverted
Next-Event-Read (read FIFO)
Trigger signal (write FIFO)
Chip enable
Abort next event in FIFO
Global reset of chip (excluding jtag)
Reset data shift register
Test pulse trigger
Selects ALICE mode (1.6V) or LHCb mode
(0V)
GTL_REF
input
bias
GTL reference voltage (~800mV) for
digital input pads
FAST_MULT
output
analog
fast multiplicity output
FAST_OR*
output
digital GTL
fast-or output
NB Digital input/output signals are NEGATIVE ‘GTL’ logic:
Logic 1 is 400mV
Logic 0 is 1.2V
This assumes a GTL reference voltage of 800mV.
The exception is ALICE, which has CMOS signal levels.
TOP PINS
supplypa1
wella1
preamp_out1
first_stage_outr1
first_stage_outl1
outl1
outr1
supplyna1
sub
supplyn1
vgtg1
sync_out_a1
analog_in1
start_a1
FIFO_IN_ALICE1
FIFO_IN_LHCB1
SHIFT_OUT1
well1
supplyp1
input
input
output
output
output
output
output
input
input
input
output
output
output
output
output
output
output
input
input
power
power
analog
analog
analog
analog
analog
power
power
power
power
digital
digital
digital
digital
digital
digital
power
power
analog supply input (1.6V)
analog well input (1.6V)
preamp signal column 1
first shaper stage out right
first shaper stage out left
shaper out left
shaper out right
analog negative supply input (0V)
substrate connection (0V)
digital negative supply (0V)
return line for GTL buffers
synchronised discriminator output
discriminator output
start for 1st delay latch
FIFO ip Alice mode
FIFO ip LHCb mode
shift reg op
digital well input (1.6V)
digital positive supply (1.6V)
supplypa2
wella2
preamp_out2
first_stage_outr2
first_stage_outl2
outl2
outr2
supplyna2
sub
supplyn2
vgtg2
sync_out_a2
analog_in2
start_a2
FIFO_IN_ALICE2
FIFO_IN_LHCB2
SHIFT_OUT2
well2
supplyp2
testgtinip
testgtinop
VgtlRef
input
input
output
output
output
output
output
input
input
input
output
output
output
output
output
output
output
input
input
input
output
input
power
power
analog
analog
analog
analog
analog
power
power
power
power
digital
digital
digital
digital
digital
digital
power
power
digital
digital
digital
analog supply input (1.6V)
analog well input (1.6V)
preamp signal column 1
first shaper stage out right
first shaper stage out left
shaper out left
shaper out right
analog negative supply input (0V)
substrate connection (0V)
digital negative supply (0V)
return line for GTL buffers
synchronised discriminator output
discriminator output
start for 1st delay latch
FIFO ip Alice mode
FIFO ip LHCb mode
shift reg op
digital well input (1.6V)
digital positive supply(1.6V)
input to test GTL ip buffer
output for GTL ip buffer
reference voltage for GTL ip buffer
supplypa3
wella3
preamp_out3
first_stage_outr3
first_stage_outl3
outl3
outr3
supplyna3
sub
supplyn3
vgtg3
sync_out_a3
analog_in3
start_a3
FIFO_IN_ALICE3
FIFO_IN_LHCB3
SHIFT_OUT3
well3
supplyp3
Vcsn
Vcsp
input
input
output
output
output
output
output
input
input
input
output
output
output
output
output
output
output
input
input
input
input
power
power
analog
analog
analog
analog
analog
power
power
power
power
digital
digital
digital
digital
digital
digital
power
power
current
current
analog supply input (1.6V)
analog well input (1.6V)
preamp signal column 1
first shaper stage out right
first shaper stage out left
shaper out left
shaper out right
analog negative supply input (0V)
substrate connection (0V)
digital negative supply (0V)
return line for GTL buffers
synchronised discriminator output
discriminator output
start for 1st delay latch
FIFO ip Alice mode
FIFO ip LHCb mode
shift reg op
digital well input (1.6V)
digital positive supply(1.6V)
ip current for n-side starving of GTL
ip current for p-side starving of GTL
testgtoutop
testgtoutip
output
input
digital
digital
op of GTL test op buffer
ip fo GTL test op buffer
bias_opbuf
bias_ipbuf
Supplypa4
Wella4
preamp_out4
first_stage_outr4
first_stage_outl4
outl4
outr14
supplyna4
sub
supplyn4
vgtg4
sync_out_a4
analog_in4
start_a4
FIFO_IN_ALICE4
FIFO_IN_LHCB4
SHIFT_OUT4
well4
input
input
input
input
output
output
output
output
output
input
input
input
output
output
output
output
output
output
output
input
current
current
power
power
analog
analog
analog
analog
analog
power
power
power
power
digital
digital
digital
digital
digital
digital
power
current bias for op stage of follower
current bias for ip stage of follower
analog supply input (1.6V)
analog well input (1.6V)
preamp signal column 1
first shaper stage out right
first shaper stage out left
shaper out left
shaper out right
analog negative supply input (0V)
substrate connection (0V)
digital negative supply (0V)
return line for GTL buffers
synchronised discriminator output
discriminator output
start for 1st delay latch
FIFO ip Alice mode
FIFO ip LHCb mode
shift reg op
digital well input (1.6V)
supplyp4
input
power
digital positive supply (1.6V)
LIST OF MODIFICATIONS
14/02/2000: Michael: Addition of list of top pins
16/02/2000: Ken: Removal of pins: Vref1, Det_guard, RESERVED