Download CPSC 352 Chapter 4: The Instruction Set Architecture

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Chapter 4: The Instruction Set Architecture
CPSC 352
Computer Organization
Chapter 4: The Instruction Set
Architecture
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Chapter 4: The Instruction Set Architecture
Chapter Contents
4.1 Hardware Components of the Instruction Set Architecture
4.2 ARC, A RISC Computer
4.3 Pseudo-Ops
4.4 Examples of Assembly Language Programs
4.5 Accessing Data in Memory—Addressing Modes
4.6 Subroutine Linkage and Stacks
4.7 Input and Output in Assembly Language
4.8 Case Study: The Java Virtual Machine ISA
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Chapter 4: The Instruction Set Architecture
The Instruction Set Architecture
• The Instruction Set Architecture (ISA) view of a machine corresponds to the machine and assembly language levels.
• A compiler translates a high level language, which is architecture
independent, into assembly language, which is architecture dependent.
• An assembler translates assembly language programs into executable binary codes.
• For fully compiled languages like C and Fortran, the binary codes
are executed directly by the target machine. Java stops the translation at the byte code level. The Java virtual machine, which is at
the assembly language level, interprets the byte codes (hardware
implementations of the JVM also exist, in which Java byte codes
are executed directly.)
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Chapter 4: The Instruction Set Architecture
The System Bus Model of a Computer
System, Revisited
• A compiled program is copied from a hard disk to the memory.
The CPU reads instructions and data from the memory, executes
the instructions, and stores the results back into the memory.
CPU
System Bus
(ALU,
Registers,
and Control)
Memory
Input and
Output (I/O)
Data Bus
Address Bus
Control Bus
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Chapter 4: The Instruction Set Architecture
Common Sizes for Data Types
• A byte is composed of 8 bits. Two nibbles make up a byte.
• Halfwords, words, doublewords, and quadwords are composed of
bytes as shown below:
Bit
0
Nibble
Byte
16-bit word (halfword)
32-bit word
64-bit word (double)
0110
10110000
11001001
10110100
01011000
11001110
01011000
11001110
00001011
10100100
128-bit word (quad)
01000110
00110101
01010101
11101110
01010101
11101110
10100110
01000100
10011001
10110000
01111000
10110000
01111000
11110010
10100101
01011000
11110011
00110101
11110011
00110101
11100110
01010001
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Chapter 4: The Instruction Set Architecture
Big-Endian and Little-Endian Formats
• In a byte-addressable machine, the smallest datum that can be
referenced in memory is the byte. Multi-byte words are stored as a
sequence of bytes, in which the address of the multi-byte word is
the same as the byte of the word that has the lowest address.
• When multi-byte words are used, two choices for the order in
which the bytes are stored in memory are: most significant byte at
lowest address, referred to as big-endian, or least significant byte
stored at lowest address, referred to as little-endian.
Byte
31 ← MSB
x
Big-Endian
x+1
x+2
LSB → 0
x+3
31 ← MSB
x+3
Little-Endian
x+2
x+1
LSB → 0
x
Word address is x for both big-endian and little-endian formats.
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Chapter 4: The Instruction Set Architecture
Memory Map for the ARC
Address
• Memory locations are ar0
ranged linearly
in consecutive
2048
order. Each
numbered locations corresponds to an
ARC word. The
unique number
that identifies 231 – 4
each word is
Disk
referred to as Terminal
Printer
its address.
Data
32 bits
Address Control
Reserved for
operating system
User Space
MEMORY
Stack pointer
Top of stack
System Stack
Bottom of stack
I/O space
Data
Out
232 – 4
byte
232 – 1
Data
In
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Chapter 4: The Instruction Set Architecture
Abstract View of a CPU
• The CPU consists of a data section containing registers and an
ALU, and a control section, which interprets instructions and effects register transfers. The data section is also known as the
datapath.
Registers
Control Unit
ALU
Datapath
(Data Section)
Control Section
System
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Chapter 4: The Instruction Set Architecture
The Fetch-Execute Cycle
• The steps that the control unit carries out in executing a program
are:
(1) Fetch the next instruction to be executed from memory.
(2) Decode the opcode.
(3) Read operand(s) from main memory, if any.
(4) Execute the instruction and store results.
(5) Go to step 1.
This is known as the fetch-execute cycle.
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An Example
Datapath
Chapter 4: The Instruction Set Architecture
Register
Source 1
(rs1)
Register
Source 2
(rs2)
From Data
Bus
Register
File
To Address
Bus
Control Unit selects
registers and ALU
function
ALU
To Data
Bus
Status to Control
Unit
Register Destination (rd)
• The ARC datapath is made up of a collection of registers known
as the register file and the arithmetic and logic unit (ALU).
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Chapter 4: The Instruction Set Architecture
The ARC ISA
• The ARC ISA is a subset of the SPARC ISA.
Mnemonic
Memory
Logic
Arithmetic
Control
Meaning
ld
Load a register from memory
st
Store a register into memory
sethi
Load the 22 most significant bits of a register
andcc
Bitwise logical AND
orcc
Bitwise logical OR
orncc
Bitwise logical NOR
srl
Shift right (logical)
addcc
Add
call
Call subroutine
jmpl
Jump and link (return from subroutine call)
be
Branch if equal
bneg
Branch if negative
bcs
Branch on carry
bvs
Branch on overflow
ba
Branch always
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Chapter 4: The Instruction Set Architecture
ARC Assembly Language Format
• The ARC assembly language format is the same as the SPARC assembly language format.
Label
lab_1:
Source
Mnemonic operands
addcc
Destination
operand
%r1, %r2, %r3
Comment
! Sample assembly code
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Chapter 4: The Instruction Set Architecture
ARC User-Visible Registers
Register 00
Register 01
%r0 [= 0]
%r1
Register 11
%r11
%r12
Register 22
Register 23
%r22
%r23
Register 12
Register 02
%r2
Register 13
%r13
Register 24
%r24
Register 03
Register 04
Register 05
Register 06
Register 07
%r3
%r4
%r5
%r6
%r7
Register14
%r14 [%sp]
Register 15
%r15 [link]
Register 16
%r16
Register 17
%r17
Register 18
%r18
Register 25
Register 26
Register 27
Register 28
Register 29
%r25
%r26
%r27
%r28
%r29
Register 08
%r8
Register 19
%r19
Register 30
%r30
Register 09
%r9
Register 20
%r20
Register 31
%r31
Register 10
%r10
Register 21
%r21
PSR
%psr
PC
%pc
32 bits
32 bits
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Chapter 4: The Instruction Set Architecture
ARC Instruction and PSR Formats
op
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
SETHI Format
0 0
rd
op2
imm22
Branch Format
0 0 0
cond
op2
disp22
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
CALL format
0 1
disp30
i
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Arithmetic
Formats
1 0
rd
op3
rs1
0 0 0 0 0 0 0 0 0
1 0
rd
op3
rs1
1
rs2
simm13
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
1 1
rd
op3
rs1
0 0 0 0 0 0 0 0 0
1 1
rd
op3
rs1
1
rs2
Memory Formats
op
Format
op2
00
01
10
11
SETHI/Branch
CALL
Arithmetic
Memory
Inst.
010 branch
100 sethi
op3 (op=10)
010000
010001
010010
010110
100110
111000
addcc
andcc
orcc
orncc
srl
jmpl
op3 (op=11)
000000 ld
000100 st
simm13
cond branch
0001
0101
0110
0111
1000
be
bcs
bneg
bvs
ba
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PSR
n z v c
Signed Formats
4-15
Signed Integer Byte
7 6
Signed Integer Halfword
0
s
15 14
Signed Integer Word
Chapter 4: The Instruction Set Architecture
s
0
s
31 30
Signed Integer Double
0
s
63 62
32
31
0
Unsigned Formats
Unsigned Integer Byte
7
0
Unsigned Integer Halfword
15
0
Unsigned Integer Word
31
0
Tagged Word
Tag
31
2 1 0
63
32
31
0
Unsigned Integer Double
Floating Point Formats
Floating Point Single
s
exponent
31 30
Floating Point Double
s
fraction
23 22
0
exponent
63 62
fraction
52 51
32
fraction
31
Floating Point Quad
s
127 126
0
exponent
fraction
112 113
96
fraction
95
64
fraction
63
32
fraction
31
0
ARC Data
Formats
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Chapter 4: The Instruction Set Architecture
ARC Pseudo-Ops
Pseudo-Op
.equ
.begin
.end
.org
.dwb
.global
.extern
.macro
Usage
Meaning
Treat symbol X as (10)16
.begin
Start assembling
.end
Stop assembling
.org 2048
Change location counter to 2048
.dwb 25
Reserve a block of 25 words
.global Y
Y is used in another module
.extern Z
Z is defined in another module
.macro M a, b, ... Define macro M with formal
X .equ
#10
.endmacro
.endmacro
.if
.if <cond>
.endif
.endif
parameters a, b, ...
End of macro definition
Assemble if <cond> is true
End of .if construct
• Pseudo-ops are instructions to the assembler. They are not part
of the ISA.
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Chapter 4: The Instruction Set Architecture
ARC Example Program
• An ARC assembly language program adds two integers:
! This programs adds two numbers
.begin
.org 2048
prog1: ld
[x],
ld
[y],
addcc %r1,
st
%r3,
jmpl
%r15
x:
15
y:
9
z:
0
.end
%r1
%r2
%r2, %r3
[z]
+ 4, %r0
!
!
!
!
!
Load x into %r1
Load y into %r2
%r3 ← %r1 + %r2
Store %r3 into z
Return
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Chapter 4: The Instruction Set Architecture
! This program sums LENGTH numbers
A More
Complex
Example
Program
! Register usage:
!
!
!
!
.begin
.org 2048
a_start
.equ 3000
loop:
ld
ld
andcc
andcc
be
addcc
addcc
%r1
%r2
%r3
%r4
%r5
–
–
–
–
–
Length of array a
Starting address of array a
The partial sum
Pointer into array a
Holds an element of a
! Start assembling
! Start program at 2048
! Address of array a
[length], %r1
[address],%r2
%r3, %r0, %r3
%r1, %r1, %r0
done
!
%r1, -4, %r1
%r1, %r2, %r4
! %r1 ← length of array a
! %r2 ← address of a
! %r3 ← 0
! Test # remaining elements
Finished when length=0
! Decrement array length
! Address of next element
ld
%r4, %r5
! %r5 ← Memory[%r4]
addcc %r3, %r5, %r3 ! Sum new element into r3
• An ARC program
sums five integers.
done:
ba
loop
jmpl
%r15 + 4, %r0 ! Return to calling routine
.org
20
a_start
a_start
length:
address:
a:
25
–10
33
–5
7
.end
! Repeat loop.
! 5 numbers (20 bytes) in a
! Start of array a
! length/4 values follow
! Stop assembling
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Chapter 4: The Instruction Set Architecture
One, Two, Three-Address Machines
• Consider how the C expression A = B*C + D might be evaluated by
each of the one, two, and three-address instruction types.
• Assumptions: Addresses and data words are two bytes in size.
Opcodes are 1 byte in size. Operands are moved to and from
memory one word (two bytes) at a time.
• Three-Address Instructions: In a three-address instruction, the expression A = B*C + D might be coded as:
mult
B, C, A
add
D, A, A
which means multiply B by C and store the result at A. (The mult
and add operations are generic; they are not ARC instructions.)
Then, add D to A and store the result at address A. The program
size is 7×2 = 14 bytes. Memory traffic is 16 + 2×(2×3) = 28 bytes.
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Chapter 4: The Instruction Set Architecture
One, Two, Three-Address Machines
• Two Address Instructions: In a two-address instruction, one of the
operands is overwritten by the result. Here, the code for the expression A = B*C + D is:
load
B, A
mult
C, A
add
D, A
The program size is now 3×(1+2×2) or 15 bytes. Memory traffic is
15 + 2×2 + 2×2×3 or 31 bytes.
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Chapter 4: The Instruction Set Architecture
One, Two, Three-Address Machines
• One Address (Accumulator) Instructions: A one-address instruction employs a single arithmetic register in the CPU, known as the
accumulator. The code for the expression A = B*C + D is now:
load
B
mult
C
add
D
store A
The load instruction loads B into the accumulator, mult multiplies C by the accumulator and stores the result in the accumulator, and add does the corresponding addition. The store instruction stores the accumulator in A. The program size is now
2×2×4 or 16 bytes, and memory traffic is 16 + 4×2 or 24 bytes.
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Addressing Modes
Chapter 4: The Instruction Set Architecture
• Four ways of computing the address of a value in memory: (1) a
constant value known at assembly time, (2) the contents of a register, (3) the sum of two registers, (4) the sum of a register and a constant. The table gives names to these and other addressing modes.
4-23
Chapter 4: The Instruction Set Architecture
Subroutine Linkage – Registers
• Subroutine linkage with registers passes parameters in registers.
! Calling routine
.
.
.
x:
y:
z:
ld
ld
call
st
.
.
.
53
10
0
[x], %r1
[y], %r2
add_1
%r3, [z]
! Called routine
! %r3 ← %r1 + %r2
add_1: addcc
jmpl
%r1, %r2, %r3
%r15 + 4, %r0
4-24
Chapter 4: The Instruction Set Architecture
Subroutine Linkage – Data Link Area
• Subroutine linkage with a data link area passes parameters in a
separate area in memory. The address of the memory area is
passed in a register (%r5 here).
! Calling routine
.
.
.
! Called routine
! x[2] ← x[0] + x[1]
st
%r1, [x]
st
%r2, [x+4]
sethi x, %r5
srl
%r5, 10, %r5
call add_2
[x+8], %r3
ld
.
.
.
! Data link area
x: .dwb 3
add_2: ld
ld
addcc
st
jmpl
%r5, %r8
%r5 + 4, %r9
%r8, %r9, %r10
%r10, %r5 + 8
%r15 + 4, %r0
4-25
Chapter 4: The Instruction Set Architecture
Subroutine Linkage – Stack
• Subroutine linkage with a stack passes parameters on a stack.
! Calling routine
.
.
.
%sp .equ
addcc
st
addcc
st
call
ld
addcc
.
.
.
%r14
%sp, -4, %sp
%r1, %sp
%sp, -4, %sp
%r2, %sp
add_3
%sp, %r3
%sp, 4, %sp
! Called routine
! Arguments are on stack.
! %sp[0] ← %sp[0] + %sp[4]
%sp .equ
add_3: ld
addcc
ld
addcc
st
jmpl
%r14
%sp, %r8
%sp, 4, %sp
%sp, %r9
%r8, %r9, %r10
%r10, %sp
%r15 + 4, %r0
4-26
Chapter 4: The Instruction Set Architecture
Line /* C program showing nested subroutine calls */
No.
Stack
Linkage
Example
• A C program
illustrates nested
function calls.
00 main()
01 {
02
int w, z;
03
w = func_1(1,2);
04
z = func_2(10);
05 }
06 int
07 int
08 {
09
10
11
12
13 }
func_1(x,y)
x, y;
14 int
15 int
16 {
17
18
19
20
21 }
func_2(a)
a;
int i, j;
i = x * x;
j = i + y;
return(j);
/*
/*
/*
/*
Local variables */
Call subroutine func_1 */
Call subroutine func_2 */
End of main routine */
/* Compute x * x + y */
/* Parameters passed to func_1 */
/* Local variables */
/* Return j to calling routine */
/* Compute a * a + a + 5 */
/* Parameter passed to func_2 */
int m, n;
/* Local variables */
n = a + 5;
m = func_1(a,n);
return(m);
/* Return m to calling routine */
4-27
Chapter 4: The Instruction Set Architecture
0
Stack
Linkage
Example
(cont’)
0
Free area
Free area
Beginning
of stack
frame
%sp
%sp
%sp
Stack
232–
4
232–
4
0
0
(a)
Initial configuration.
w and z are already on the
stack. (Line 00 of program.)
Free area
• (a-f) Stack behavior during
execution of
the program
shown in previous slide.
0
%sp
j
i
%r15
2
1
(d)
Stack space is reserved for
func_1 local variables i
and j. (Line 09 of
program.)
2
1
%r15
2
1
Stack
Stack
(b)
Calling routine pushes
arguments onto stack,
prior to func_1 call.
(Line 03 of program.)
232–
4
(c)
After the call, called
routine saves PC of calling
routine (%r15) onto stack.
(Line 06 of program.)
0
Stack
frame for
func_1
Free area
%sp
Stack
232–
4
Free area
3
Free area
%sp
Stack
232–
4
(e)
Return value from
func_1 is placed on
stack, just prior to return.
(Line 12 of program.)
Stack
232–
4
(f)
Calling routine pops
func_1 return value
from stack. (Line 03 of
program.)
4-28
Chapter 4: The Instruction Set Architecture
0
func_1
stack frame
0
0
Free area
Stack Linkage
Example
(cont’)
• (g-k) Stack behavior during
execution of
the C program
shown previously.
n
m
%r15
10
j
i
%r15
15
10
n
m
%r15
10
Stack
Stack
Free area
%sp
%sp
Stack
frame for
func_2
232–
4
232–
4
0
0
(g)
A stack frame is created
for func_2 as a result of
function call at line 04 of
program.
(h)
A stack frame is created
for func_1 as a result of
function call at line 19 of
program.
115
(j)
func_2 places return
value on stack. (Line 20 of
program.)
func_2
stack frame
232–
4
Stack
232–
4
115
n
m
%r15
10
Stack
(i)
func_1 places return
value on stack. (Line
12 of program.)
%sp
Stack
232–
4
%sp
Free area
Free area
%sp
Free area
(k)
Program finishes. Stack is restored
to its initial configuration. (Lines
04 and 05 of program.)
4-29
Chapter 4: The Instruction Set Architecture
Address
Input and
Output for
the ISA
0
216
Data
32 bits
Reserved for built-in
bootstrap and graphics
routines
Add-in video memory #1
217
Add-in video memory #2
219
Unused
• Memory map for
the ARC, showing
memory mapped
I/O.
222
Working Memory
Stack pointer
Top of stack
System Stack
223 – 4
Bottom of stack
FFFFEC16 Screen Flash
FFFFF016 Touchscreen x
FFFFF416 Touchscreen y
I/O space
224 – 4
byte
224 – 1
4-30
Chapter 4: The Instruction Set Architecture
Touchscreen I/O Device
• A user selecting an object on a touchscreen:
LEDs
(sources)
User breaks
beams
Detector
4-31
Chapter 4: The Instruction Set Architecture
Read X register.
Read Y register.
Flowchart for
I/O Device
Compare old X and Y
values to new values
No
• Flowchart illustrating the
control structure of a program that tracks a
touchscreen.
Did X or Y
change?
Yes
Flash screen
Update X and Y
registers
4-32
Chapter 4: The Instruction Set Architecture
Java Virtual Machine Architecture
32 bits
Byte Codes
0
Java Stack
.
.
.
.
.
.
m
32 bits
Control
0
Operand stack
.
.
.
Local variables
8 bits
Java Execution Engine
0
Constant pool
.
.
.
Stack top index
65,535
State variables
.
.
.
Thread state
Registers
Stack frame
n
Current method pointer
Current method’s class pointer
Current method’s constant pool pointer
Stack frame pointer
Program counter
4-33
Chapter 4: The Instruction Set Architecture
// This is file add.java
public class add {
public static void main(String args[]) {
int x=15, y=9, z=0;
z = x + y;
}
}
Java
Program
and
Compiled
Class
File
0000
0010
0020
0030
0040
0050
0060
0070
0080
0090
00a0
00b0
00c0
00d0
00e0
00f0
0100
0110
0120
0130
cafe
0a00
0100
5374
743e
7461
7074
6265
5661
6365
6464
616e
6e00
1100
0000
0000
0008
0008
0003
0000
babe
0200
1628
7269
0100
6e74
696f
7254
7269
4669
2e6a
672f
2100
0600
0d10
0001
0006
0000
b100
0100
0003
040c
5b4c
6e67
0443
5661
6e73
6162
6162
6c65
6176
4f62
0100
0100
0f3c
000b
000c
001d
0000
0100
002d
0007
6a61
3b29
6f64
6c75
0100
6c65
6c65
0100
6101
6a65
0200
0800
1009
0000
0002
0001
0100
0d00
0012
0005
7661
5601
6501
6501
0f4c
0100
7301
0361
0010
6374
0000
0000
3d03
000e
0001
0001
0b00
0000
0700
0100
2f6c
0006
000d
000a
696e
0e4c
000a
6464
6a61
0100
0000
2d00
3e1b
0003
0007
0000
0000
0200
0e07
0328
616e
3c69
436f
4578
654e
6f63
536f
0100
7661
046d
0200
0200
1c60
0000
0005
0005
0600
0f00
0010
2956
672f
6e69
6e73
6365
756d
616c
7572
0861
2f6c
6169
0900
0400
3eb1
0004
0001
2ab7
0100
................
.............()V
...([Ljava/lang/
String;)V...<ini
t>...Code...Cons
tantValue...Exce
ptions...LineNum
berTable...Local
Variables...Sour
ceFile...add...a
dd.java...java/l
ang/Object...mai
n...............
................
................
................
................
................
................
..............
4-34
Chapter 4: The Instruction Set Architecture
A Java Class File
18 items in constant pool
Tag = 7 (Class)
Minor version
Name index = 14
Major
Tag = 7 (Class)
Magic number
version
Name
Location
0000
cafe babe 0003 002d 0012 0700 0e07 0010 index = 16
Tag = 10 (Methodref)
Name and type
index = 4
Class
index = 2
0010
0050
Tag = 1 (Utf)
Length =
“ptions”
15 bytes
0060
“([Ljava/lang/”
0070
Length = 6 bytes
“<ini”
“Variables”
0080
5374 7269 6e67 3b29 5601 0006 3c69 6e69
0090
743e 0100 0443 6f64 6501 000d 436f 6e73
Tag = 1 (Utf)
Length =
10 bytes “Sour”
5661 7269 6162 6c65 7301 000a 536f 7572
Tag = 1 (Utf)
Tag = 1 (Utf)
Length =
Length =
“ceFile”
3 bytes “add”
8 bytes
Tag = 1 (Utf)
Tag = 1 (Utf)
Length =
Length =
“t>”
4 bytes “Code”
13 bytes “Cons”
0040
Tag = 1 (Utf)
Length =
14 bytes “Local”
6265 7254 6162 6c65 0100 0e4c 6f63 616c
0100 1628 5b4c 6a61 7661 2f6c 616e 672f
“String;)V”
“LineNum”
7074 696f 6e73 0100 0f4c 696e 654e 756d
“berTable”
Tag = 1 (Utf)
0030
7461 6e74 5661 6c75 6501 000a 4578 6365
0a00 0200 040c 0007 0005 0100 0328 2956
Tag = 1 (Utf)
Length = 22 bytes
0020
Tag = 12 (NameAndType)
Name index = 7
Type index = 5
Tag = 1 (Utf)
Length = 3 bytes
“()V”
Tag = 1 (Utf)
Length =
10 bytes “Exce”
“tantValue”
6365 4669 6c65 0100 0361 6464 0100 0861
“a”
4-35
Chapter 4: The Instruction Set Architecture
A Java Class File (Cont’)
Tag = 1 (Utf)
Length =
16 bytes
“dd.java”
00a0
“java/l”
6464 2e6a 6176 6101 0010 6a61 7661 2f6c
00f0
0000 0001 000b 0000 000e 0003 0000 0004
616e 672f 4f62 6a65 6374 0100 046d 6169
0100
Access flags: ACC_PUBLIC | ACC_STATIC
Access flags: ACC_PUBLIC | ACC_SUPER
Superclass: java/lang/Object
This
Interface
Fields count
class: add
count
“n”
Methods count
Access flags: ACC_PUBLIC
Start PC / Start PC /
Name index “<init>”
Line no.
Line no.
Type index “()V”
Attributes
0008 0006 000c 0002 0001 0007 0005 0001 count
Attribute name index: “Code” Code count
=5
Max stack = 2
Max
locals = 1
Bytes count = 29
CODE
0110
0008 0000 001d 0001 0001 0000 0005 2ab7
“ang/Object”
00b0
Attribute name index: “LineNumberTable” Start PC /
Attributes count
Line no.
Bytes
Lines
Handlers
count = 14 count = 3
count
Tag = 1 (Utf)
Length =
4 bytes “mai”
Attribute name index: “LineNumberTable”
Handlers count Attributes
Bytes
Lines
count
CODE
count = 6
count = 1
00c0
6e00 2100 0100 0200 0000 0000 0200 0900
00d0
Name index “<init>”
Type index “([Ljava/lang/String;)V”
Attribute name index: “Code”
Attributes
0120
0003 b100 0000 0100 0b00 0000 0600 0100
Bytes count = 45
Max stack = 2
count
Attributes count
Max locals = 4
Attribute name index “SourceFile”
1100 0600 0100 0800 0000 2d00 0200 0400
Start PC /
Source file index:
Bytes count = 2
Line no.
bipush (0x10) 15 (0x0f) iconst_0 (0x03)
istore_3 (0x3e)
“add.java”
istore_1 (0x3c)
iload_1 (0x1b)
bipush (0x10) 9 (0x09)
iload_2 (0x1c)
Code
0130
0000 0100 0100 0d00 0000 0200 0f00
istore_2 (0x3d)
iadd (0x60)
count = 13
istore_3 (0x3e)
0000 0d10 0f3c 1009 3d03 3e1b 1c60 3eb1 return (0xb1)
00e0
4-36
Chapter 4: The Instruction Set Architecture
Byte Code for Java Program
• Disassembled byte code for previous Java program.
Location
0x00e3
0x00e4
0x00e5
0x00e6
0x00e7
0x00e8
0x00e9
0x00ea
0x00eb
0x00ec
0x00ed
0x00ee
0x00ef
Code
0x10
0x0f
0x3c
0x10
0x09
0x3d
0x03
0x3e
0x1b
0x1c
0x60
0x3e
0xb1
Mnemonic
bipush
15
istore_1
bipush
9
istore_2
iconst_0
istore_3
iload_1
iload_2
iadd
istore_3
return
Meaning
Push next byte onto stack
Argument to bipush
Pop stack to local variable 1
Push next byte onto stack
Argument to bipush
Pop stack to local variable 2
Push 0 onto stack
Pop stack to local variable 3
Push local variable 1 onto stack
Push local variable 2 onto stack
Add top two stack elements
Pop stack to local variable 3
Return