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M.TECH DEGREE EXAMINATION, 2012
MODEL QUESTION
Second Semester (Regular-2011 Admissions)
Electronics and Communication Engineering, VLSI and Embedded Systems
MEC VE 201 - ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS
Time: 3Hrs
Maximum Marks: 100
ANSWER ALL QUESTIONS
1. a) Write a short note on body effect and channel length modulation
(15)
b) Derive an expression for output resistance in CS stage with source
degeneration?
(10)
OR
2. a) Derive an expression for the voltage gain of circuit in fig.
(13)
b) Discuss on folded cascade circuit and its large signal characteristics
(12)
3. a) Write a short note on active current mirrors
(15)
b) In the circuit of fig, (W/L )1,2 ,3,4 = 50/0.5 and ISS =1mA. What is the small
signal differential gain? For Vin,cm = 1.5 V what is the maximum allowable output
swing?
(10)
OR
4. a) Write a short note on cascode current mirrors
(12)
b) In the circuit of fig, all transistors have a (W/L ) of 50/0.5 and M3 and M4 are
to operate in deep triode region with an on resistance of 2 Kῼ, Assuming Id5 = 20
µA and λ = ϒ = 0. Calculate the input common mode level that yields such
resistance. Sketch Vout1 and Vout2 as Vin1 and Vin2 vary differentially from 0 to
VDD.
(13)
5. a) Discuss about the need for compensation in op-amp
(12)
b) For the circuit in fig., (W/L )1,2 = 50/0.5, (W/L )3,4 = 10/0.5, ISS =100µA, K=2,
CL=0 and RD is implemented by an NFET having (W/L ) = 50/0.5, estimate the
poles and zeros of the circuit. Assume the amplifier is driven by an ideal voltage
source.
(13)
OR
6. (a) Design the op amp of fig. for the following requirements; maximum
differential swing = 4V, Total power dissipation = 6 mW,Iss = 0.5 mA.
(15)
(b) Discuss on pole zero compensation
(10)
7. a) Describe the noises in integrated circuits
(15)
(10)
b) Derive the expression of noise bandwidth
OR
8. a) Illustrate the following
i) Bipolar transistor noise generators
ii) MOS transistor noise generators
b) Explain the noise in operational amplifiers.
(15)
(10)
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