Download Nonideal Transistor

Introduction to
CMOS VLSI
Design
Nonideal Transistors
Outline
 Transistor I-V Review
 Nonideal Transistor Behavior
– Velocity Saturation
– Channel Length Modulation
– Body Effect
– Leakage
– Temperature Sensitivity
 Process and Environmental Variations
– Process Corners
CMOS VLSI Design
2
Ideal Transistor I-V
 Shockley 1st order transistor models


0

 
Vds
I ds    Vgs  Vt 
2


2


Vgs  Vt 


2
Vgs  Vt
V V  V
 ds
ds
dsat

Vds  Vdsat
cutoff
linear
saturation
Vdsat = Vgs - Vt
CMOS VLSI Design
3
Ideal nMOS I-V Plot
 180 nm TSMC process
 Ideal Models
–  = 155(W/L) mA/V2
– Vt = 0.4 V
– VDD = 1.8 V
 = mnCox(W/L)
Ids (mA)
400
300
Vgs = 1.5
200
Vgs = 1.2
100
0
CMOS VLSI Design
Vgs = 1.8
Vgs = 0.9
Vgs = 0.6
0
0.3
0.6
0.9
1.2
1.5
1.8
Vds
4
Simulated nMOS I-V Plot
 180 nm TSMC process
 BSIM 3v3 SPICE models
– very elaborate model derived from the underlying
Ids (mA)
device physics
 What differs?
250
Vgs = 1.8
200
Vgs = 1.5
150
Berkeley Short-Channel
IGFET Model (BSIM)
Vgs = 1.2
100
Vgs = 0.9
50
Vgs = 0.6
0
0
0.3
0.6
0.9
1.2
1.5
Vds
CMOS VLSI Design
5
Simulated nMOS I-V Plot
 180 nm TSMC process
 BSIM 3v3 SPICE models
 What differs?
I (mA)
– Less ON current
250
– No square law
200
– Current increases
150
in saturation
100
ds
Vgs = 1.8
Vgs = 1.5
Vgs = 1.2
Vgs = 0.9
50
Vgs = 0.6
0
0
0.3
0.6
0.9
1.2
1.5
Vds
CMOS VLSI Design
6
Velocity Saturation
 We assumed carrier velocity is proportional to E-field
– v = mElat = mVds/L
 At high fields, this ceases to be true
– Carriers scatter off atoms  
– Velocity reaches vsat
• Electrons: 6-10 x 106 cm/s
• Holes: 4-8 x 106 cm/s  / 2
– Better model
sat
sat
μElat
v
 vsat  μEsat
Elat
1
Esat
CMOS VLSI Design
slope = m
0
0
Esat
2Esat
3Esat
Elat
7
Velocity Sat I-V Effects
 Ideal transistor ON current increases with V2
2
W Vgs  Vt 

I ds  mCox
 Vgs  Vt 
L
2
2
2
 Velocity-saturated ON current increases with V
I ds  CoxW Vgs  Vt  vmax
 Real transistors are partially velocity saturated
– Approximate with a-power law model
– Ids  Va
– 1 < a < 2 determined empirically
CMOS VLSI Design
8
a-Power Model
 0

V

I ds   I dsat ds
Vdsat


 I dsat
Vgs  Vt
cutoff
I dsat  Pc
Vds  Vdsat
linear
Vds  Vdsat
saturation

V

2
gs
 Vt 
a
Vdsat  Pv Vgs  Vt 
a /2
Simulated
a-law
Shockley
Ids (mA)
400
300
Vgs = 1.8
200
Vgs = 1.5
CMOS VLSI Design
100
Vgs = 1.2
0
Vgs = 0.9
Vgs = 0.6
0
0.3
0.6
0.9
1.2
1.5
1.8 V
ds
9
Channel Length Modulation
 Reverse-biased p-n junctions form a depletion region
– Region between n and p with no carriers
– Width of depletion Ld region grows with reverse bias
V
V
GND
– Leff = L – Ld
Source
Gate
Drain
Depletion Region
 Shorter Leff gives more current
Width: L
– Ids increases with Vds
– Even in saturation
L
n+
n+
DD
DD
d
Leff
p GND
CMOS VLSI Design
bulk Si
10
Chan Length Mod I-V
Ids (mA)
400
I ds 

V

2
gs
 Vt  1  lVds 
2
Vgs = 1.8
300
Vgs = 1.5
200
Vgs = 1.2
100
0
0
Vgs = 0.9
Vgs = 0.6
0.3
0.6
0.9
1.2
1.5
1.8 Vds
 l = channel length modulation coefficient
– not feature size
– Empirically fit to I-V characteristics
CMOS VLSI Design
11
Body Effect
 Vt: gate voltage necessary to invert channel
 Increases if source voltage increases because
source is connected to the channel
 Increase in Vt with Vs is called the body effect
CMOS VLSI Design
12
Body Effect Model
Vt  Vt 0  g

fs  Vsb  fs

 fs = surface potential at threshold
fs  2vT ln
NA
ni
– Depends on doping level NA
– And intrinsic carrier concentration ni
 g = body effect coefficient
g
tox
 ox
2q si N A
2q si N A 
Cox
CMOS VLSI Design
13
OFF Transistor Behavior
 What about current in cutoff?
I
 Simulated results
1 mA
 What differs?
Sub100 mA
threshold
– Current doesn’t go 10 mA Region
1 mA
to 0 in cutoff
100 nA
ds
10 nA
Saturation
Region
Vds = 1.8
Subthreshold
Slope
1 nA
100 pA
10 pA
Vt
0
0.3
0.6
0.9
1.2
1.5
1.8
Vgs
CMOS VLSI Design
14
Leakage Sources
 Subthreshold conduction
– Transistors can’t abruptly turn ON or OFF
 Junction leakage
– Reverse-biased PN junction diode current
 Gate leakage
– Tunneling through ultra-thin gate dielectric
 Subthreshold leakage is the biggest source in
modern transistors
CMOS VLSI Design
15
Subthreshold Leakage
 Subthreshold leakage exponential with Vgs
Vgs Vt
I ds  I ds 0e
nvT
Vds

v
 1  e T




I ds 0   vT2 e1.8
 n is process dependent, typically 1.4-1.5
CMOS VLSI Design
16
DIBL
 Drain-Induced Barrier Lowering
– Drain voltage also affect Vt
Vt   Vt  Vds
VVV
ttds
– High drain voltage causes subthreshold leakage
to ________.
CMOS VLSI Design
17
DIBL
 Drain-Induced Barrier Lowering
– Drain voltage also affect Vt
Vt   Vt  Vds
VVV
ttds
– High drain voltage causes subthreshold leakage
to increase.
CMOS VLSI Design
18
Junction Leakage
 Reverse-biased p-n junctions have some leakage
 VvD

T
I D  I S  e  1




 Is depends on doping levels
– And area and perimeter of diffusion regions
– Typically < 1 fA/mm2
p+
n+
n+
p+
p+
n+
n w ell
p substrate
CMOS VLSI Design
19
Gate Leakage
 Carriers may tunnel thorough very thin gate oxides
 Predicted tunneling current (from
[Song01])
10
9
VDD trend
0.6 nm
0.8 nm
2
JG (A/cm )
10 6
tox
10 3
1.0 nm
1.2 nm
10 0
1.5 nm
1.9 nm
10 -3
10 -6
 Negligible for older processes10
0
 May soon be critically important
-9
CMOS VLSI Design
0.3
0.6
0.9
1.2
1.5
1.8
VDD
20
Temperature Sensitivity
 Increasing temperature
– Reduces mobility
– Reduces Vt
 ION ___________ with temperature
 IOFF ___________ with temperature
CMOS VLSI Design
21
Temperature Sensitivity
 Increasing temperature
– Reduces mobility
– Reduces Vt
 ION decreases with temperature
 IOFF increases with temperature
I ds
increasing
temperature
Vgs
CMOS VLSI Design
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So What?
 So what if transistors are not ideal?
– They still behave like switches.
 But these effects matter for…
– Supply voltage choice
– Logical effort
– Quiescent power consumption
– Pass transistors
– Temperature of operation
CMOS VLSI Design
23
Parameter Variation
fast
 Transistors have uncertainty in parameters
– Process: Leff, Vt, tox of nMOS and pMOS
– Vary around typical (T) values
 Fast (F)
– Leff: ______
– Vt: ______
– tox: ______
 Slow (S): opposite
nMOS
 Not all parameters are independent
for nMOS and pMOS
FF
pMOS
SF
TT
slow
slow
CMOS VLSI Design
FS
SS
fast
24
Parameter Variation
FF
pMOS
fast
 Transistors have uncertainty in parameters
– Process: Leff, Vt, tox of nMOS and pMOS
– Vary around typical (T) values
SF
 Fast (F)
TT
– Leff: short
– Vt: low
– tox: thin
SS
 Slow (S): opposite
slow
nMOS
 Not all parameters are independent
for nMOS and pMOS
slow
FS
CMOS VLSI Design
fast
25
Environmental Variation
 VDD and T also vary in time and space
 Fast:
– VDD: ____
– T: ____
Corner
Voltage
Temperature
1.8
70 C
F
T
S
CMOS VLSI Design
26
Environmental Variation
 VDD and T also vary in time and space
 Fast:
– VDD: high
– T: low
Corner
Voltage
Temperature
F
1.98
0C
T
1.8
70 C
S
1.62
125 C
CMOS VLSI Design
27
Process Corners
 Process corners describe worst case variations
– If a design works in all corners, it will probably
work for any variation.
 Describe corner with four letters (T, F, S)
– nMOS speed
– pMOS speed
– Voltage
– Temperature
CMOS VLSI Design
28
Important Corners
 Some critical simulation corners include
Purpose
nMOS
pMOS
VDD
Temp
Cycle time
Power
Subthreshold
leakage
Pseudo-nMOS
CMOS VLSI Design
29
Important Corners

Some critical simulation corners include
Purpose
nMOS
pMOS
VDD
Temp
Cycle time,
timimg
specification.
conservative
S
S
S
S
Power,DC power
comsumption,
race
conditions,etc
F
F
F
F
Subthreshold
leakage, noise
analysis
F
F
F
S
Pseudo-nMOS
and ratioed
circuits
S
F
F
F
CMOS VLSI Design
30