Download LECTURE 170 – INTUITIVE ANALYSIS OF ANALOG CIRCUITS

Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-1
LECTURE 170 – INTUITIVE ANALYSIS OF ANALOG CIRCUITS
(READING: AH – 191-193)
Objective
The objective of this presentation is:
1.) Illustrate how to perform a small-signal, midband analysis from the schematic
2.) Introduce the Miller technique and the approximate method of solving for two poles
Outline
• Key concepts in CMOS analog IC circuit analysis
• Intuitive approach
• Examples
• Summary
ECE 6412 - Analog Integrated Circuit Design - II
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-2
IMPORTANT RELATIONSHIPS FOR CMOS ANALOG IC DESIGN
1.) Square law relationship:
K’W
iD = 2L (vGS - VT)2
2.) Small-signal transconductance formula:
2K’WID
L
3.) Small-signal simplification:
gm ≈ 10gmbs ≈ 100gds
4.) Saturation relationship:
gm =
VDS(sat) =
2ID
K’(W/L)
ECE 6412 - Analog Integrated Circuit Design - II
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-3
An Intuitive Method of Small Signal Analysis
Small signal analysis is used so often in analog circuit design that it becomes desirable to
find faster ways of performing this important analysis.
Intuitive Analysis (or Schematic Analysis)
Technique:
1.) Identify the transistor(s) that convert the input voltage to current (these transistors
are called transconductance transistors).
2.) Trace the currents to where they flow into an equivalent resistance to ground.
3.) Multiply this resistance by the current to get the voltage at this node to ground.
4.) Repeat this process until the output is reached.
Simple Example:
VDD
VDD
R1
gm1vin
vin
M2
vo1 gm2vo1
vout
R2
M1
Fig. 5.2-10C
vo1 = -(gm1vin) R1 → vout = -(gm2vo1)R2
→
vout = (gm1R1gm2R2)vin
ECE 6412 - Analog Integrated Circuit Design - II
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-4
Intuitive Analysis of the Current-Mirror Load Differential Amplifier
VDD
M4
M3
gm1vid gm1vid
2
2
M1 gm1vid gm2vid
2
2
+
vid
2 M5
VBias
+
vid
rout
+
M2
vid
vout
+ 2
Fig. 5.2-11
1.)
2.)
3.)
i1 = 0.5gm1vid and i2 = -0.5gm2vid
i3 = i1 = 0.5gm1vid
i4 = i3 = 0.5gm1vid
4.)
1
The resistance at the output node, rout, is rds2||rds4 or gds2 + gds4
gm1vin
gm2vin
vout
gm1
5.) ∴ vout = (0.5gm1vid +0.5gm2vid )rout = g +g = g +g ⇒ v = g +g
ds2 ds4
ds2 ds4
in
ds2 ds4
ECE 6412 - Analog Integrated Circuit Design - II
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-5
Some Concepts to Help Extend the Intuitive Method of Small-Signal Analysis
1.) Approximate the output resistance of any cascode circuit as
Rout ≈ (gm2rds2)rds1
where M1 is a transistor cascoded by M2.
2.) If there is a resistance, R, in series with the source of the transconductance transistor,
let the effective transconductance be
gm
gm(eff) = 1+gmR
Proof:
gm2(eff)vin
gm2(eff)vin
M2
gm2vgs2 iout
+ vgs2 -
M2
vin
vin
M1 vin
rds1
rds1
Small-signal model
VBias
Fig. 5.2-11A
vin
∴ vgs2 = vg2 - vs2 = vin - (gm2rds1)vgs2 ⇒ vgs2 = 1+gm2rds1
gm2vin
Thus, iout = 1+g r = gm2(eff) vin
m2 ds1
ECE 6412 - Analog Integrated Circuit Design - II
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-6
Miller Two-Stage Op Amp
VDD
M6
M3
M4
Cc
vout
M1
M2
vin
Assume proper
M5
common mode +
input voltage VBias
-
ECE 6412 - Analog Integrated Circuit Design - II
M7
VSS
Fig. 170-01
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-7
Miller Two-Stage Op Amp
VDD
M6
M3
M4
Cc
vout
vin
M1
+
vin
2 -
M2
Assume proper
M5
common mode +
input voltage VBias
-
vin
2+
M7
Fig. 170-01
VSS
ECE 6412 - Analog Integrated Circuit Design - II
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-8
Miller Two-Stage Op Amp
VDD
M6
M3
gm1vin
2
vin
M1
+
vin
2 -
Assume proper
M5
common mode +
input voltage VBias
-
ECE 6412 - Analog Integrated Circuit Design - II
M4
Cc
vout
gm2vin
2
M2
vin
2+
M7
VSS
Fig. 170-01
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-9
Miller Two-Stage Op Amp
VDD
gm1vin
2
gm1vin
2
M3
gm1vin
2
vin
M1
+
vin
2 -
Assume proper
M5
common mode +
input voltage VBias
-
M4
M6
Cc
vout
gm2vin
2
M2
vin
2+
M7
Fig. 170-01
VSS
ECE 6412 - Analog Integrated Circuit Design - II
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-10
Miller Two-Stage Op Amp
VDD
gm1vin
2
gm1vin
2
M3
gm1vin
2
vin
M1
+
vin
2 -
Assume proper
M5
common mode +
input voltage VBias
-
ECE 6412 - Analog Integrated Circuit Design - II
M4 Ro1=rds2||rds4
vo1 +
M6
Cc
vout
gm2vin
2
M2
vin
2+
M7
VSS
Fig. 170-01
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-11
Miller Two-Stage Op Amp
VDD
gm1vin
2
gm1vin
2
M3
M4 Ro1=rds2||rds4
gm1vin
2
vin
vo1 +
Cc
gm2vin
2
M2
vin
2+
M1
+
vin
2 -
Assume proper
M5
common mode +
input voltage VBias
-
M6
gm6vo1
vout
Rout=rds6||rds7
M7
Fig. 170-01
VSS
vout  gm1   -gm6 
-gm1gm6
vin = gds2+gds4 gds6+gds7 = (gds2+gds4)(gds6+gds7)
ECE 6412 - Analog Integrated Circuit Design - II
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-12
Folded-Cascode Op Amp
VDD
VBias
M10
M3
M1 M2
M8
vin
M11
M9
vout
M6 M7
VBias
VBias
M4 M5
ECE 6412 - Analog Integrated Circuit Design - II
VSS
Fig. 170-02
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-13
Folded-Cascode Op Amp
VDD
VBias
M10
M3
vin + vin
2
+2
M1 M2 -
M8
vin
M11
M9
vout
M6 M7
VBias
VBias
M4 M5
VSS
ECE 6412 - Analog Integrated Circuit Design - II
Fig. 170-02
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-14
Folded-Cascode Op Amp
VDD
VBias
vin
M10
M3
vin + vin
2
+2
M1 M2 gm1vin
gm2vin
2
2
M8
M11
M9
vout
M6 M7
VBias
VBias
M4 M5
ECE 6412 - Analog Integrated Circuit Design - II
VSS
Fig. 170-02
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-15
Folded-Cascode Op Amp
VDD
VBias
vin
M11
M10
M3
vin + vin
2
+2
M1 M2 gm1vin
gm2vin
2
2
M8
M9
vout
M6 M7
VBias
gm1vin
2
gm2vin
2
VBias
M4 M5
VSS
ECE 6412 - Analog Integrated Circuit Design - II
Fig. 170-02
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-16
Folded-Cascode Op Amp
VDD
VBias
vin
M11
M10
M3
vin + vin
2
+2
M1 M2 gm1vin
gm2vin
2
2
gm1vin M8
2
M9
vout
M6 M7
VBias
gm1vin
2
gm2vin
2
gm2vin
2
VBias
M4 M5
ECE 6412 - Analog Integrated Circuit Design - II
VSS
Fig. 170-02
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-17
Folded-Cascode Op Amp
VDD
VBias
vin
M11
gm1vin
2
M10
M3
gm1vin
2
gm1vin M8
2
vin + vin
2
+2
M1 M2 gm1vin
gm2vin
2
2
M9
vout
M6 M7
VBias
gm2vin
2
gm1vin
2
gm2vin
2
VBias
M4 M5
VSS
Fig. 170-02
ECE 6412 - Analog Integrated Circuit Design - II
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
Page 170-18
Folded-Cascode Op Amp
VDD
VBias
vin
M11
gm1vin
2
M10
gm1vin
2
gm1vin M8
2
M3
vin + vin
2
+2
M1 M2 gm1vin
gm2vin
2
2
M6 M7
VBias
gm1vin
2
M9
vout
Rout = [gm9rds9rds11]
gm2vin ||[gm7rds7(rds2||rds5)]
2
gm2vin
2
VBias
M4 M5
VSS
Fig. 170-02
vout gm1 gm2
vin =  2 + 2 Rout = gm1{(gm9rds9rds11)||[gm7rds7(rds2||rds5)]}
ECE 6412 - Analog Integrated Circuit Design - II
© P.E. Allen - 2002
Lecture 170 – 1 Stage Frequency Response (1/10/02)
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Page 170-19
SUMMARY
Intuitive method is quick and simple
Intuitive method is approximate (misses the unbalance of the folded cascode)
Intuitive method does not give any information about frequency response
The intuitive method can be used with BJT circuits assuming β >>1 and including rπ in
the resistance calculations
ECE 6412 - Analog Integrated Circuit Design - II
© P.E. Allen - 2002