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Si and CdTe Detector Readout ASIC in 0.35µm CMOS for
Energetic Electron Spectroscopy for Taranis Mission
K.W.
1
Wong ,
O.
2
Bernal
,
3
1
1
1
F. Bouyjou , G. Orttner , O. Chassela , M. Bassas ,
1
1
1
P. Devoto , P.L. Blelly and J.A. Sauvaud
G.
1
Roudil ,
H.
2
Tap ,
1Institut
de Recherche en Astrophysique et Planétologie of Centre National de la Recherche Scientifique, Toulouse France
2Laboratoire d’Analyse et d’Architecture des Systèmes of Centre National de la Recherche Scientifique and INP of Université de Toulouse, Toulouse France
3Service d’Electronique, des Détecteurs et d’Informatique, Gif-sur-Yvette Cedex F-91191, France
Mission objective
Layout considerations
Taranis Mission objective is the study of lightings occurring
above large storm clouds. These phenomena are called transient
luminous events (TLEs). They are sometimes accompanied by
terrestrial gamma-ray flashes (TGFs) as well as burst of
precipitated and accelerated electrons. Their mechanisms and
their effects are what the mission is trying to understand.
IDEE ASIC objective
Maximum detection
37 fC
ENC
Counting Rate
Peaking time
2400 e600 kHz
60 ns
Electronic
Box
Figure: Transistor Level Schematic of the AOP
Figure: IDEE Sensor
Radioactive source test
1088 e40kHz
3 µs
The analog front end is followed by a peak
detector and a SAR ADC. The SAR ADC is
the same for both type of channel.
Non detrimental overshoot
CdTe data clock
Si channel data clock
Si channel data
(extracted)
Si 0
2,5
0,1
Si 1
Si 2
2
319keV
Si 3
1,5
Si 4
1
0,5
0,01
0
0
0,001
0
10
20
30
40
bin (BCD)
50
60
Figure: 207Bi - (electron) and X source
measurement on Si channels
10
70
20
30
40
bin (BCD)
50
60
70
Figure: 133Ba - (electron) and X source source
measurement on Si channels
SEE tests
Test Facility: RADEF, JYFL, Jyvaskyla, Finland
For SEL characterization, 2 samples were exposed with krypton ion and a tilt angle of 37 deg.
for an effective LET of 40 MeV/(mg/cm²) at ambient temperature.
CdTe data
Si peak detector output
Si channel data
482keV
The SEL current is 91mA (versus 21mA
nominal current).
The delatch circuit (on board) has properly
detected the latchup event.
Simulation results
Si Front end output
3
Si0
Si1
Si2
Si3
Si4
1
Count/sec
The required integration time for CdTe
channel being of 3µs, the signal undershoot
is detrimental to the frequency performance
of the channel.
It is created by the 2nd pole of the CSA-PS
chain. A PZC circuit is thus implemented by
Figure: Simplified Schematic of CdTe Analog Front End adding an extra resistor Rz in parallel to the
pulse shaper derivation circuit (Cd, Rd).
CdTe channel performance
The core circuit of the AOP is similar to the
Minimum detection
6 fC
one used for Si channels.
ENC
Counting Rate
Peaking time
 The HV board generates the 100 and 300V
necessary for Si and CdTe detectors biasing.
 The FPGA board encapsulates the detected
energy in the appropriate data frame.
 The LVC board provides voltage supplies for
the other boards.
The detector head is made of 8 CdTe detectors
placed behind a strip of 5 Silicon pixels. The
centered Silicon pixel is about 40 times smaller
than the others. It will be used alone during the
South Atlantic Anomaly crossing that would
saturate the instrument otherwise.
HV, FPGA and LVC boards
10
160 fC
ADC
A 207Bi radioactive source has been placed in front of the detection head, centered in XY. The
207Bi 482keV  - desintegration peak is detected on Si1 and Si3 channels (the closest to the
source). A 976keV Beta- peak would be expected on the CdTe detector, but the Si detector placed
between the source and the CdTe prevents having meaningful CdTe spectra. A 133Ba source has
also been characterized showing the cluster of electron desintegration around 319keV.
CdTe analog front end
Maximum detection
PD
5 Si channels
count/sec
2 fC
Analog
FE
IDEE ASIC is tested in the electronic box
coupled with the detector head.
Detection
Head
Minimum detection
Peak Detect
Interface Test Between ASIC and Detectors
IDEE ASIC
The Si detector front end makes use of a RC
CSA followed by a semi gaussian shaper.
The operational amplifier (AOP) core circuit is
a two stage differential input/single ended
output amplifier making use of a cascoded
current mirror. The transistor size and biasing is
optimized for noise and bandwidth performance.
ADC
PD
Figure: Microphotograph of IDEE ASIC
Si analog front end
Si channel performance
Analog FE
To further reduce crosstalk, power supply
of the analog part of the channel is isolated
from the peak detection and ADC..
IDEE (Instrument Détecteur d’Electron Energétique) instrument is dedicated to energetic
electron spectrometry in the range from 70keV to 4MeV. To achieve this goal, two types of
detectors are used: Si detectors for the 70keV to 700keV energy range and CdTe detectors for the
300keV to 4MevVrange.
The ASIC has the objective to digitize the energy response from 5 Si detectors and 8CdTe
detectors with 6-bit resolution each. These 13 channels are integrated on the same chip.
Figure: Simplified Schematic of Si Analog Front End
8 CdTe channels
The circuit has been implemented in AMS
0.35µm HV CMOS technology.
This technology has a triple well option
allowing isolation of transistors from the
bulk.
=> advantage in terms of noise and
crosstalk reduction.
CH1 (yellow) ASIC current (factor 30.3)
CH2 (blue)
Latchup Flag
CH3 (pink)
ASIC voltage supply
CdTe peak detector output
CdTe Front end output
Acknowledgments
The authors would like to thank Laurence Boissier from the french space agency CNES for her
support.