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Lesson 10
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Design Flow & Design Tools
Types of ASICs
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A full-custom IC includes some (possibly all) logic cells that are
customized and all mask layers that are customized. A microprocessor
is an example of a full-custom IC—designers spend many hours
squeezing the most out of every last square micron of microprocessor
chip space by hand. It allows designers to include analog circuits,
optimized memory cells. Full-custom ICs are the most expensive to
manufacture and to design. The manufacturing lead time (the time it
takes just to make an IC—not including design time) is typically eight
weeks for a full-custom IC.
Semicustom ASICs , in which all of the logic cells are predesigned and
some (possibly all) of the mask layers are customized. Using
predesigned cells from a cell library makes our lives as designers
much, much easier. There are two types of semicustom ASICs:
standard-cell–based ASICs & gate-array–based ASICs.
programmable ASICs ,in which all of the logic cells are predesigned
and none of the mask layers are customized. There are two types of
programmable ASICs: the programmable logic device and, the newest
member of the ASIC family, the field-programmable gate array.
Full-Custom ASICs
•In a full-custom ASIC an engineer designs some or all of the logic
cells, circuits, or layout specifically for one ASIC. This means the
designer abandons the approach of using pretested and
precharacterized cells for all or part of that design. It makes sense
to take this approach only if there are no suitable existing cell
libraries available that can be used for the entire design. This
might be because existing cell libraries are not fast enough, or the
logic cells are not small enough or consume too much power. You
may need to use full-custom design if the ASIC technology is new
or so specialized that there are no existing cell libraries or because
the ASIC is so specialized that some circuits must be custom
designed. Fewer and fewer full-custom ICs are being designed
because of the problems with these special parts of the ASIC.
There is one growing member of this family, though, the mixed
analog/digital ASIC.
Library-Cell Design
The optimum cell layout for each process generation changes because the
design rules for each ASIC vendor’s process are always slightly different—
even for the same generation of technology. For example, two companies
may have very similar 0.35 m m CMOS process technologies, but the thirdlevel metal spacing might be slightly different. If a cell library is to be used
with both processes, we could construct the library by adopting the most
stringent rules from each process. A library constructed in this fashion may
not be competitive with one that is constructed specifically for each process.
Even though ASIC vendors prize their design rules as secret, it turns out that
they are similar—except for a few details. Unfortunately, it is the details that
stop us moving designs from one process to another. Unless we are a very
large customer it is difficult to have an ASIC vendor change or waive design
rules for us. We would like all vendors to agree on a common set of design
rules. This is, in fact, easier than it sounds. The reason that most vendors
have similar rules is because most vendors use the same manufacturing
equipment and a similar process. It is possible to construct a highest
common denominator library that extracts the most from the current
manufacturing capability. Some library companies and the large Japanese
ASIC vendors are adopting this approach.
Library-Cell Design, Cont
Each standard cell in a library is rectangular with the same height but
different widths. The bounding box ( BB ) of a logic cell is the
smallest rectangle that encloses all of the geometry of the cell. The
cell BB is normally determined by the well layers. Cell connectors or
terminals (the logical connectors ) must be placed on the cell
abutment box ( AB ). The physical connector (the piece of metal to
which we connect wires) must normally overlap the abutment box
slightly, usually by at least 1 l , to assure connection without leaving
a tiny space between the ends of two wires. The standard cells are
constructed so they can all be placed next to each other horizontally
with the cell ABs touching (we abut two cells). When a library
developer creates a gate-array, standard-cell, or datapath library,
there is a trade-off between using wide, high-drive transistors that
result in large cells with high-speed performance and using smaller
transistors that result in smaller cells that consume less power. A
performance-optimized library with large cells might be used for
ASICs in a high-performance workstation, for example. An areaoptimized library might be used in an ASIC for a battery-powered
portable computer.
Gate-Array Design
Each logic cell or macro in a gate-array library is predesigned using
fixed tiles of transistors known as the gate-array base cell (or just
base cell ). We call the arrangement of base cells across a whole chip
in a complete gate array the gate-array base. ASIC vendors offer a
selection of bases, with a different total numbers of transistors on
each base. For example, if our ASIC design uses 48k equivalent gates
and the ASIC vendor offers gate arrays bases with 50k-, 75k-, and
100k-gates, we will probably have to use the 75k-gate base it is
unlikely 96 percent of the transistors on the 50k-gate base).
We isolate the transistors on a gate array from one another either
with thick field oxide (in the case of oxide-isolated gate arrays) or by
using other transistors that are wired permanently off (in gateisolated gate arrays). Figure 3.14 (a) shows a base cell for a gateisolated gate array . This base cell has two transistors: one p channel and one n -channel. When these base cells are placed next to
each other, the n -diffusion and p -diffusion layers form continuous
strips that run across the entire chip broken only at the poly gates
that cross at regularly spaced intervals (Figure 3.14b). The metal
interconnect spacing determines the separation of the transistors.
The metal spacing is determined by the design rules for the metal
and contacts.
In Figure 3.14 (c) we have shown all possible locations
for a contact in the base cell. There is room for 21
contacts in this cell and thus room for 21 interconnect
lines running in a horizontal direction (we use m1 running
horizontally). We say that there are 21 horizontal tracks
in this cell or that the cell is 21 tracks high. In a similar
fashion the space that we need for a vertical interconnect
(m2) is called a vertical track . The horizontal and vertical
track widths are not necessarily equal, because the
design rules for m1 and m2 are not always equal.
We isolate logic cells from each other in gate-isolated
gate arrays by connecting transistor gates to the supply
bus—hence the name, gate isolation . If we connect the
gate of an n -channel transistor to V SS , we isolate the
regions of n -diffusion on each side of that transistor (we
call this an isolator transistor or device, or just isolator).
Similarly if we connect the gate of a p -channel transistor
to V DD , we isolate adjacent p -diffusion regions.
FIGURE 3.14 The construction of a gate-isolated gate array. (a) The onetrack-wide base cell containing one p -channel and one n -channel transistor.
(b) Three base cells: the center base cell is being used to isolate the base
cells on either side from each other. (c) A base cell including all possible
contact positions (there is room for 21 contacts in the vertical direction,
showing the base cell has a height of 21 tracks).
Oxide-isolated gate arrays often contain four transistors in the base cell: the two n -channel transistors share an n diffusion strip and the two p -channel transistors share a p -diffusion strip. This means that the two n -channel
transistors in each base cell are electrically connected in series, as are the p -channel transistors. The base cells are
isolated from each other using oxide isolation . During the fabrication process a layer of the thick field oxide is left
in place between each base cell and this separates the p -diffusion and n -diffusion regions of adjacent base cells.
Figure 3.15 shows an oxide-isolated gate array . This cell contains eight transistors (which occupy six vertical
tracks) plus one-half of a single track that contains the well contacts and substrate connections that we can
consider to be shared by each base cell.
FIGURE 3.15 An oxide-isolated gate-array base cell. The figure shows two base cells, each containing eight
transistors and two well contacts. The p -channel and n -channel transistors are each 4 tracks high (corresponding
to the width of the transistor). The leftmost vertical track of the left base cell includes all 12 possible contact
positions (the height of the cell is 12 tracks). As outlined here, the base cell is 7 tracks wide (we could also consider
the base cell to be half this width).
Figure 3.16 shows a base cell in which the gates of the n -channel and p -channel transistors are connected on the
polysilicon layer. Connecting the gates in poly saves contacts and a metal interconnect in the center of the cell
where interconnect is most congested. The drawback of the preconnected gates is a loss in flexibility in cell design.
Implementing memory and logic based on transmission gates will be less efficient using this type of base cell, for
example.
FIGURE 3.16 This oxide-isolated gate-array base cell is 14 tracks high and 4 tracks wide. VDD (tracks 3 and 4) and
GND (tracks 11 and 12) are each 2 tracks wide. The metal lines to the left of the cell indicate the 10 horizontal
routing tracks (tracks 1, 2, 5–10, 13, 14). Notice that the p -channel and n -channel polysilicon gates are tied
together in the center of the cell. The well contacts are short, leaving room for a poly cross-under in each base cell.
Figure 3.17 shows the metal personalization for a D flip-flop macro in a gate-isolated gate array using a base cell
similar to that shown in Figure 3.14 (a). This macro uses 20 base cells, for a total of 40 transistors, equivalent to
10 gates. The gates of the base cells shown in Figures 3.14 – 3.16 are bent. The bent gate allows contacts to the
gates to be placed on the same grid as the contacts to diffusion. The polysilicon gates run in the space between
adjacent metal interconnect lines. This saves space and also simplifies the routing software.
There are many trade-offs that determine the gate-array base cell height. One factor is the number of wires that
can be run horizontally through the base cell. This will determine the capacity of the routing channel formed from
an unused row of base cells. The base cell height also determines how easy it is to wire the logic macros since it
determines how much space for wiring is available inside the macros.
FIGURE 3.17 An example of a flip-flop macro in a gate-isolated gate-array library. Only the first-level metallization
and contact pattern (the personalization) is shown on the right, but this is enough information to derive the
schematic. The base cell is shown on the left. This macro is 20 tracks wide.
There are other factors that determine the width of the base-cell transistors. The widths of the p -channel and n channel transistors are slightly different in Figure 3.14 (a). The p -channel transistors are 6 tracks wide and the n channel transistors are 5 tracks wide. The ratio for this gate-array library is thus approximately 1.2. Most gatearray libraries are approaching a ratio of 1.
ASIC designers are using ever-increasing amounts of RAM on gate arrays. It is inefficient to use the normal base
cell for a static RAM cell and the size of RAM on an embedded gate array is fixed. As an alternative we can change
the design of the base cell. A base cell designed for use as RAM has extra transistors (either four—two n -channel
and two p -channel—or two n -channel; usually minimum width) allowing a six-transistor RAM cell to be built using
one base cell instead of the two or three that we would normally need. This is one of the advantages of the CBA
(cell-based array) base cell shown in Figure 3.18 .
FIGURE 3.18 The SiARC/Synopsys cell-based array (CBA) basic cell.
Programmable ASICs
There are two types of programmable ASICs: programmable logic devices
(PLDs) and field-programmable gate arrays (FPGAs). PLDs started as small
devices that could replace a handful of TTL parts, and they have grown to
look very much like their younger relations, the FPGAs. designer, can
program yourself. An IC foundry produces FPGAs with some connections
missing. You perform design entry and simulation. Next, special software
creates a string of bits describing the extra connections required to make
your design—the configuration file . You then connect a computer to the chip
and program the chip to make the necessary connections according to the
configuration file. There is no customization of any mask level for an FPGA,
allowing the FPGA to be manufactured as a standard part in high volume.
FPGAs are popular with microsystems designers because they fill a gap
between TTL and PLD design and modern, complex, and often expensive
ASICs. FPGAs are ideal for prototyping systems or for low-volume
production. FPGA vendors do not need an IC fabrication facility to produce
the chips; instead they contract IC foundries to produce their parts. Being
fabless relieves the FPGA vendors of the huge burden of building and running
a fabrication plant Instead FPGA companies put their effort into the FPGA
architecture and the software, where it is much easier to make a profit than
building chips. They often sell the chips through distributors, but sell design
software and any necessary programming hardware directly.
Programmable ASICs, Cont
All FPGAs have certain key elements in common. All FPGAs have a regular array of
basic logic cells that are configured using a programming technology . The chip inputs
and outputs use special I/O logic cells that are different from the basic logic cells. A
programmable interconnect scheme forms the wiring between the two types of logic
cells. Finally, the designer uses custom software, tailored to each programming
technology and FPGA architecture, to design and implement the programmable
connections. The programming technology in an FPGA determines the type of basic
logic cell and the interconnect scheme. The logic cells and interconnection scheme, in
turn, determine the design of the input and output circuits as well as the programming
scheme.
The programming technology may or may not be permanent. You cannot undo the
permanent programming in one-time programmable ( OTP ) FPGAs. Reprogrammable
or erasable devices may be reused many times. programming technologies:
The Antifuse
The Static RAM
The EPROM &EEPROM
The Antifuse
The Static
RAM
The Xilinx SRAM (static RAM) configuration cell. The outputs of the crosscoupled inverter (configuration control) are connected to the gates of pass
transistors or transmission gates. The cell is programmed using the WRITE
and DATA lines.
The EPROM &EEPROM
ASIC Design Flow
ASIC Design Flow
1.Design entry. Enter the design into an ASIC design system, either using a
hardware description language ( HDL ) or schematic entry .
2.Logic synthesis. Use an HDL (VHDL or Verilog) and a logic synthesis tool to
produce a netlist —a description of the logic cells and their connections.
3.System partitioning. Divide a large system into ASIC-sized pieces.
4.Prelayout simulation. Check to see if the design functions correctly.
5.Floorplanning. Arrange the blocks of the netlist on the chip.
6.Placement. Decide the locations of cells in a block.
7.Routing. Make the connections between cells and blocks.
8.Extraction. Determine the resistance and capacitance of the interconnect.
9.Postlayout simulation. Check to see the design still works with the added loads
of the interconnect.
Steps 1–4 are part of logical design , and steps 5–9 are part of physical design . There
is some overlap. For example, system partitioning might be considered as either
logical or physical design. To put it another way, when we are performing system
partitioning we have to consider both logical and physical factors.
Types of Simulation
Simulators are usually divided into the following categories or
simulation modes :
•Behavioral simulation
•Functional simulation
•Static timing analysis
•Gate-level simulation
•Switch-level simulation
•Transistor-level or circuit-level simulation
Simulation, cont.
This list is ordered from high-level to low-level simulation (high-level being
more abstract, and low-level being more detailed). Proceeding from highlevel to low-level simulation, the simulations become more accurate, but
they also become progressively more complex and take longer to run. There
are several ways to create an imaginary simulation model of a system. One
method models large pieces of a system as black boxes with inputs and
outputs. This type of simulation (often using VHDL or Verilog) is called
behavioral simulation . Functional simulation ignores timing and includes
unit-delay simulation , which sets delays to a fixed value (for example, 1 ns).
Once a behavioral or functional simulation predicts that a system works
correctly, the next step is to check the timing performance. At this point a
system is partitioned into ASICs and a timing simulation is performed for
each ASIC separately (otherwise the simulation run times become too long).
One class of timing simulators employs timing analysis that analyzes logic in
a static manner, computing the delay times for each path. This is called static
timing analysis because it does not require the creation of a set of test (or
stimulus) vectors (an enormous job for a large ASIC). Timing analysis works
best with synchronous systems whose maximum operating frequency is
determined by the longest path delay between successive flip-flops. The path
with the longest delay is the critical path .
Simulation, cont.
Logic simulation or gate-level simulation can also be used to check the timing
performance of an ASIC. In a gate-level simulator a logic gate or logic cell (NAND,
NOR, and so on) is treated as a black box modeled by a function whose variables are
the input signals. The function may also model the delay through the logic cell. Setting
all the delays to unit value is the equivalent of functional simulation. If the timing
simulation provided by a black-box model of a logic gate is not accurate enough, the
next, more detailed, level of simulation is switch-level simulation which models
transistors as switches—on or off. Switch-level simulation can provide more accurate
timing predictions than gate-level simulation, but without the ability to use logic-cell
delays as parameters of the models. The most accurate, but also the most complex
and time-consuming, form of simulation is transistor-level simulation . A transistorlevel simulator requires models of transistors, describing their nonlinear voltage and
current characteristics.
Each type of simulation normally uses a different software tool. A mixed-mode
simulator permits different parts of an ASIC simulation to use different simulation
modes. For example, a critical part of an ASIC might be simulated at the transistor
level while another part is simulated at the functional level. Simulation is used at many
stages during ASIC design. Initial prelayout simulations include logic-cell delays but no
interconnect delays. Estimates of capacitance may be included after completing logic
synthesis, but only after physical design is it possible to perform an accurate post
layout simulation