Download Voltage or Current References

Voltage or Current References
Requirements of a Reference Circuit:
• Should be independent of power supply
• Should be independent of temperature
• Should be independent of processing variations
• Should be independent of noise
Voltage or Current References
Requirements of a Reference Circuit:
• Should be independent of power supply
• Should be independent of temperature
• Should be independent of processing variations
• Should be independent of noise
Sensitivity:
Vref
SV =
dd
( D Vref / Vref )
/ ( D Vdd / Vdd )
Voltage or Current References
Requirements of a Reference Circuit:
• Should be independent of power supply
• Should be independent of temperature
• Should be independent of processing variations
• Should be independent of noise
Sensitivity:
Vref
SV =
dd
( D Vref / Vref )
/ ( D Vdd / Vdd )
If sensitivity = 1, then 10% change in Vdd
results in a 10% in Vref
Simple Bias Circuits
Vdd
Vout
GND
Typically using
a potentiometer
Simple Bias Circuits
Vdd
Vout
GND
Typically using
a potentiometer
Vref
SV = 1
dd
Simple Bias Circuits
Vdd
Transistor-based
resistive divider
Vout
Vdd
Vout
GND
Typically using
a potentiometer
Vref
SV = 1
dd
GND
Simple Bias Circuits
Vdd
Transistor-based
resistive divider
Vout
Vdd
Vout
GND
Typically using
a potentiometer
Vref
SV = 1
dd
GND
If KN = KP and VTN = |VTP|
Vref
SV = 1
dd
Simple Bias Circuits
Vdd
Transistor-based
resistive divider
Vout
Vdd
Vout
GND
Typically using
a potentiometer
Vref
SV = 1
dd
GND
If KN = KP and VTN = |VTP|
Vref
SV = 1
dd
Typically poor Power Supply Rejection (low PSRR)
Bias Circuits involving Diodes
MOSFET Source
Vdd
R
Iout
Vout
GND
Current Source
GND
Bias Circuits involving Diodes
MOSFET Source
BJT Source
Vdd
Vdd
R
Iout
R
Vout
Vout
GND
Current Source
GND
GND
Bias Circuits involving Diodes
MOSFET Source
BJT Source
Vdd
Vdd
R
Iout
R
Vout
Vout
GND
Current Source
GND
GND
Significant Power Supply Rejection (higher PSRR)
Output Voltage Sensitivity
BJT Source
Vdd
Small-Signal
model:
Vdd
R
R
Vref
Vref
1/gm
GND
GND
Output Voltage Sensitivity
BJT Source
Vdd
Small-Signal
model:
Vdd
R
Vref
R
gm
Vref
Vref
1/gm
GND
GND
= Vdd / (1 + gm R)
= (Vdd0 – Vref0)/ R UT
Output Voltage Sensitivity
BJT Source
Vdd
Small-Signal
model:
Vdd
R
Vref
R
gm
Vref
= (Vdd0 – Vref0)/ R UT
Vref
Vref (1 + (Vdd0
1/gm
GND
= Vdd / (1 + gm R)
GND
– Vref0)/ UT ) = Vdd
Vref
SV = (Vref / Vdd) (Vdd0 / Vref0)
dd
= (Vdd0/Vref0)/(1 + (Vdd0–Vref0)/UT )
Output Voltage Sensitivity
BJT Source
Vref
SV = (Vref / Vdd) (Vdd0 / Vref0)
Vdd
dd
= (Vdd0/Vref0)/(1 + (Vdd0–Vref0)/UT )
R
Vref
GND
Output Voltage Sensitivity
BJT Source
Vref
SV = (Vref / Vdd) (Vdd0 / Vref0)
Vdd
dd
= (Vdd0/Vref0)/(1 + (Vdd0–Vref0)/UT )
R
Vref
Vdd0–Vref0
Vref
>> UT
SV = (Vdd0/ (Vdd0–Vref0)) (UT / Vref0)
dd
GND
Output Voltage Sensitivity
BJT Source
Vref
SV = (Vref / Vdd) (Vdd0 / Vref0)
Vdd
dd
= (Vdd0/Vref0)/(1 + (Vdd0–Vref0)/UT )
R
Vref
Vdd0–Vref0
>> UT
Vref
SV = (Vdd0/ (Vdd0–Vref0)) (UT / Vref0)
dd
~1
GND
Output Voltage Sensitivity
BJT Source
Vref
SV = (Vref / Vdd) (Vdd0 / Vref0)
Vdd
dd
= (Vdd0/Vref0)/(1 + (Vdd0–Vref0)/UT )
R
Vref
Vdd0–Vref0
>> UT
Vref
SV = (Vdd0/ (Vdd0–Vref0)) (UT / Vref0)
dd
~1
GND
With Vref0 ~ 0.65,
Vref
SV = 0.04
dd
Bias Circuits involving Diodes
Vdd
R
Vout
R1
Allows wider
variation of
output voltage
GND
R2
GND
Significant Power Supply Rejection (high PSRR)
Breakdown Diode Reference
Breakdown Diode Reference
Breakdown Diode Reference
V
V
 V

v  V

 rZ  VDD


 Z  R VBV
 REF  DD    ref DD 
SVREF

 V  V
DD
v V  r

DD 
 REF
 dd   BV
Big Issue: Very noisy output voltage
Bootstrapped Reference
Vdd
Vdd
M4
M3
Vout2
Iref
Vout1
M1
M2
GND
R
GND
AI = (W/L)1 / (W/L)2
Bootstrapped Reference
Vdd
Vdd
M4
M3
Vout2
Iref
Vout1
M1
M2
V
R
GND
GND
AI = (W/L)1 / (W/L)2
Bootstrapped Reference
Vdd
Vdd
M4
M3
Vout2
In subthreshold (or BJTs):
V = UT ln(AI) = Iref R
Iref
Vout1
M1
M2
V
R
GND
AI = (W/L)1 / (W/L)2
GND
Iref = UT ln(AI) / R
Bootstrapped Reference
Vdd
Vdd
Vdd
M4
M3
AI = (W/L)1 / (W/L)2
Vout2
Iref
Iref
Iref
Vout1
M1
Iref = UT ln(AI) / R
M2
V
R
GND
In subthreshold (or BJTs):
V = UT ln(AI) = Iref R
GND
GND
Bootstrapped Reference
Bootstrapped Reference
Bootstrapped Reference
Startup Circuit
Bootstrapped Reference
Bootstrapped Reference
Bootstrapped Reference
Startup Circuit