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LT1641-1/LT1641-2 Positive High Voltage Hot Swap Controllers DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LT®1641-1/LT1641-2 are 8-pin Hot SwapTM controllers that allow a board to be safely inserted and removed from a live backplane. Using an external N-channel pass transistor, the board supply voltage can be ramped up at a programmable rate. A high side switch driver controls an N-channel gate for supply voltages ranging from 9V to 80V. Allows Safe Board Insertion and Removal from a Live Backplane Controls Supply Voltage from 9V to 80V Programmable Analog Foldback Current Limiting High Side Drive for an External N-Channel Latched Operation Mode (LT1641-1) Automatic Retry (LT1641-2) User Programmable Supply Voltage Power-Up Rate Undervoltage Lockout Overvoltage Protection Both are available in 8-Lead SO Package The chips feature a programmable analog foldback current limit circuit. If the chips remain in current limit for more than a programmable time, the N-channel pass transistor is either latched off (LT1641-1) or is set to automatically restart after a time-out delay (LT1641-2). APPLICATIO S ■ ■ ■ ■ The PWRGD output indicates when the output voltage, sensed by the FB pin, is within tolerance. The ON pin provides programmable undervoltage lockout. Hot Board Insertion Electronic Circuit Breaker Industrial High Side Switch/Circuit Breaker 24V/48V Industrial/Alarm Systems The LT1641-1/LT1641-2 are available in the 8-lead SO package. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATIO 24V Input Voltage Application RS 0.01 VIN 24V Q1 IRF530 V OUT SHORT PIN R1 49.9k 1% D1 CMPZ 5248B R5 10 5% CL R3 59k 1% C1 R6, 10nF 1k, 5% V CC *SMAT70A SENSE R7 24k 5% GATE FB ON LT1641-1/LT1641-2 R2 3.4k 1% PWRGD TIMER R4 3.57k 1% PWRGD GND C2 0.68ᄉ F GND *DIODES, INC. 1641-1 TA01 164112fc 1 LT1641-1/LT1641-2 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO (Note 1) TOP VIEW Input Voltage (FB, ON) ............................... – 0.3V to 60V Output Voltage (PWRGD) ........................ – 0.3V to 100V Output Voltage (GATE) ............................ – 0.3V to 100V Operating Temperature Range LT1641-1C, LT1641-2C ........................... 0ᄚ C to 70 ᄚ C LT1641-1I, LT1641-2I ........................ – 40ᄚ C to 85ᄚ C Storage Temperature Range ................. – 65ᄚ C to 150 ᄚ C Lead Temperature (Soldering, 10 sec) .................. 300ᄚ C ON 1 8 VCC FB 2 7 SENSE PWRGD 3 6 GATE GND 4 5 TIMER S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125ᄚ C, JA = 110ᄚ C/W S8 PART MARKING 16411 16411I 16412 16412I ORDER PART NUMBER LT1641-1CS8 LT1641-1IS8 LT1641-2CS8 LT1641-2IS8 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25ᄚ C. Vcc = 24V SYMBOL PARAMETER VCC CONDITIONS MIN VCC Operating Range ● ICC VCC Supply Current ● VLKO VCC Undervoltage Lockout VFBH FB Pin High Voltage Threshold ON = 3V TYP 9 MAX UNITS 80 V 2 5.5 mA ● 7.5 8.3 8.8 V FB Low to High Transition ● 1.280 1.313 1.345 V FB High to Low Transition ● 1.221 1.233 1.245 VFBL FB Pin Low Voltage Threshold VFBHST FB Pin Hysteresis Voltage IINFB FB Pin Input Current VFB = GND VFB FB Pin Threshold Line Regulation 9V VCC 80V ● 0.05 mV/V VSENSETRIP SENSE Pin Trip Voltage (VCC – VSENSE) VFB = 0V VFB = 1V ● ● 8 39 12 47 17 55 mV mV IGATEUP GATE Pin Pull-Up Current Charge Pump On, VGATE = 7V ● –5 – 10 – 20 ᄉA IGATEDN GATE Pin Pull-Down Current Any Fault Condition, VGATE = 2V ● 35 70 100 mA VGATE External N-Channel Gate Drive VGATE – VCC, VCC = 10.8V to 20V VCC = 20V to 80V ● ● 4.5 10 18 18 V V ITIMERUP TIMER Pin Pull-Up Current VTIMER = 0V ● – 24 – 80 – 132 ᄉA ITIMERON TIMER Pin Pull-Down Current VTIMER = 1V ● 1.5 3 5 ᄉA 1.280 1.313 1.345 V 1.221 1.233 1.245 V 80 V mV –1 ᄉA VONH ON Pin High Threshold ON Low to High Transition ● VONL ON Pin Low Threshold ON High to Low Transition ● VONHYST ON Pin Hysteresis IINON ON Pin Input Current VON = GND –1 ᄉA VOL PWRGD Output Low Voltage IO = 2mA IO = 4mA ● ● 0.4 2.5 V V IOH PWRGD Pin Leakage Current VPWRGD = 80V ● 10 ᄉA 2 80 mV LT1641-1/LT1641-2 164112fc 3 LT1641-1/LT1641-2 AC ELECTRICAL CHARACTERISTICS TA = 25ᄚ C, VCC = 24V SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tPHLON ON Low to GATE Low Figures 1, 2 6 ᄉs tPLHON ON High to GATE High Figures 1, 2 1.7 ᄉs tPHLFB FB Low to PWRGD Low Figures 1, 3 3.2 ᄉs tPLHFB FB High to PWRGD High Figures 1, 3 tPHLSENSE (VCC – SENSE) High to GATE Low Figures 1, 4 ᄉs 1.5 0.5 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 1 ᄉs 2 Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. TYPICAL PERFOR A CE CHARACTERISTICS ICC vs VCC 3.0 48V 85ᄚ C 3.0 1.250 2.5 25ᄚ C 2.5 FB PIN LOW VOLTAGE THRESHOLD (V) 3.5 24V –45ᄚ C 2.0 ICC (mA) ICC (mA) FB Pin Low Voltage Threshold vs Temperature ICC vs Temperature 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 20 40 60 VCC (V) 80 0 –50 100 –25 0 25 50 TEMPERATURE (ᄚ C) 75 1641-1 G01 0.090 1.320 0.085 1.315 1.310 1.305 1.300 1.295 1.220 1.215 1.210 1.205 –25 0 25 50 TEMPERATURE (ᄚ C) 75 1641-1 G04 –8 –9 –10 0.060 –11 0.055 0.040 –50 VCC = 48V –7 0.065 0.045 100 –6 0.070 1.285 IGATE Pull Up vs Temperature –5 VCC = 48V 0.075 0.050 100 1641-1 G03 0.080 1.290 75 1.225 IGATE PULL UP (ᄉ A) FB PIN HYSTERESIS (V) FB PIN HIGH VOLTAGE THRESHOLD (V) 0.095 1.325 0 25 50 TEMPERATURE (ᄚ C) 1.230 1.200 –50 100 0.100 VCC = 48V –25 1.235 FB Pin Hysteresis vs Temperature 1.335 1.280 –50 1.240 1641-1 G02 FB Pin High Voltage Threshold vs Temperature 1.330 VCC = 48V 1.245 –12 –25 0 25 50 TEMPERATURE (ᄚ C) 75 100 1641-1 G05 –13 –50 –25 0 25 50 TEMPERATURE (ᄚ C) 75 100 1641-1 G06 164112fc 4 LT1641-1/LT1641-2 TYPICAL PERFOR A CE CHARACTERISTICS Gate Drive vs Temperature –40 16 15 14 GATE DRIVE (VGATE – VCC) (V) VCC = 48V 13 12 11 10 9 8 VCC = 10.8V 7 6 –50 TA = 25ᄚ C 14 12 10 8 0 25 50 TEMPERATURE (ᄚ C) 75 0 100 20 40 VCC (V) 60 14 TA = –45ᄚ C TA = 0ᄚ C 10 TA = 25ᄚ C TA = 85ᄚ C 50 VCC (V) 70 1.325 1.320 1.315 1.310 1.305 1.300 1.295 1.290 –50 90 1.235 1.233 1.231 1.229 1.227 1.225 –25 0 25 50 TEMPERATURE (ᄚ C) 75 –50 100 SENSE PIN REGULATION VOLTAGE (mV) PWRGD V OUT LOW (V) 0.080 0.070 0.060 14 12 10 8 TA = –45ᄚ 6 4 C TA = 25ᄚ 2 0.050 C 0 100 1641-1 G13 75 100 50 16 75 0 25 50 TEMPERATURE (ᄚ C) SENSE Pin Regulation Voltage vs VFEEDBACK VCC = 48V 18 0.090 0 25 50 TEMPERATURE (ᄚ C) –25 1641-1 G12 20 VCC = 48V 100 VCC = 48V 1.237 PWRGD VOUT Low vs ILOAD 0.100 75 ON Pin Low Voltage Threshold vs Temperature 1641-1 G11 ON Pin Voltage Hysteresis vs Temperature –25 0 25 50 TEMPERATURE (ᄚ C) 1.223 1.285 1641-1 G10 –50 –25 1.239 VCC = 48V 1.330 6 30 –90 1641-1 G09 ON PIN LOW VOLTAGE THRESHOLD (V) ON PIN HIGH VOLTAGE THRESHOLD (V) TIMER PIN PULL UP CURRENT (ᄉ A) 80 1.335 10 –80 ON Pin High Voltage Threshold vs Temperature 16 8 –70 1641-1 G08 TIMER Pin Pull Up Current vs VCC 12 –60 –110 –50 6 –25 VCC = 48V –100 1641-1 G07 ON PIN LOW VOLTAGE HYSTERESIS (V) TIMER PIN PULL UP CURRENT (ᄉ A) 16 GATE DRIVE (VGATE – VCC) (V) TIMER Pin Pull Up Current vs Temperature Gate Drive vs VCC 10 30 50 ILOAD (mA) TA = 85ᄚ C 70 90 1641-1 G14 VCC = 48V TA = 25ᄚ C 45 40 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 VFEEDBACK (V) 0.8 1 1641-1 G15 5 LT1641-1/LT1641-2 164112fc 6 LT1641-1/LT1641-2 PI FU CTIO S ON (Pin 1): The ON pin is used to implement undervoltage lockout. When the ON pin is pulled below the 1.233V Highto-Low threshold voltage, an undervoltage condition is detected and the GATE pin is pulled low to turn the MOSFET off. When the ON pin rises above the 1.313V Low-to-High threshold voltage, the MOSFET is turned on again. Pulsing the ON pin low after a current limit fault will reset the fault latch and allow the part to turn back on. FB (Pin 2): Power Good Comparator Input. It monitors the output voltage with an external resistive divider. When the voltage on the FB pin is lower than the High-to-Low threshold of 1.233V, the PWRGD pin is pulled low and released when the FB pin is pulled above the 1.313V Lowto-High threshold. GATE (Pin 6): The High Side Gate Drive for the External N-Channel. An internal charge pump guarantees at least 10V of gate drive for supply voltages above 20V and 4.5V gate drive for supply voltages between 10.8V and 20V. The rising slope of the voltage at the GATE is set by an external capacitor connected from the GATE pin to GND and an internal 10 ᄉ A pull-up current source from the charge pump output. When the current limit is reached, the GATE pin voltage will be adjusted to maintain a constant voltage across the sense resistor while the timer capacitor starts to charge. If the TIMER pin voltage exceeds 1.233V, the GATE pin will be pulled low. The FB pin also effects foldback current limit (see Figure 7 and related discussion). The GATE pin is pulled to GND whenever the ON pin is pulled low, the VCC supply voltage drops below the 8.3V undervoltage lockout threshold or the TIMER pin rises above 1.233V. PWRGD (Pin 3): Open Collector Output to GND. The PWRGD pin is pulled low whenever the voltage at the FB pin falls below the High-to-Low threshold voltage. It goes into a high impedance state when the voltage on the FB pin exceeds the Low-to-High threshold voltage. An external pull-up resistor can pull the pin to a voltage higher or lower than VCC. SENSE (Pin 7): The Current Limit Sense Pin. A sense resistor must be placed in the supply path between VCC and SENSE. The current limit circuit will regulate the voltage across the sense resistor (VCC – VSENSE) to 47mV when VFB is 0.5V or higher. If VFB drops below 0.5V, the voltage across the sense resistor decreases linearly and stops at 12mV when VFB is 0V. GND (Pin 4): Chip Ground. To defeat current limit, short the SENSE pin to the VCC pin. TIMER (Pin 5): Timing Input. An external timing capacitor at this pin programs the maximum time the part is allowed to remain in current limit. VCC (Pin 8): The Positive Supply Input ranges from 9V to 80V for normal operation. ICC is typically 2mA. An internal undervoltage lockout circuit disables the chip for inputs less than 8.3V. When the part goes into current limit, an 77ᄉ A pullup current source starts to charge the timing capacitor. When the voltage on the TIMER pin reaches 1.233V, the GATE pin is pulled low; the pull-up current will be turned off and the capacitor is discharged by a 3ᄉ A pull-down current. When the TIMER pin falls below 0.5V, the GATE pin either turns on automatically (LT1641-2) or turns on once the ON pin is pulsed low to reset the internal fault latch (LT1641-1). If the ON pin is not cycled low, the GATE pin remains latched off. Use no less than 1.5nF for the timing capacitor, C2. 164112fc 7 LT1641-1/LT1641-2 BLOCK DIAGRA VCC SENSE VP VP GEN FB – 12mV ~ 47mV CHARGE PUMP AND GATE DRIVER + + REF GEN 0.5V GATE + – PWRGD 1.233V 1.233V – + ON – VCC – UNDERVOLTAGE LOCKOUT + 8.3V LOGIC + 0.5V – VP 80ᄉ A + 1.233V – TIMER 3ᄉ A 1641-1 BD GND TEST CIRCUIT ON V+ 5V V CC FB SENSE PWRGD GATE + – 24V 10nF 5k GND TIMER 1641-1 F01 Figure 1 164112fc 8 LT1641-1/LT1641-2 TI I G DIAGRA S 1.313V 1.313V 1.233V ON FB tPLHON 1.233V tPLHFB tPHLON tPHLFB 1V 1V PWRGD GATE 5V 1V 1641-1 F03 1641-1 F02 Figure 2. ON to GATE Timing Figure 3. FB to PWRGD Timing VCC – SENSE 47mV tPHLSENSE V CC GATE 1641-1 F04 Figure 4. SENSE to GATE Timing APPLICATIO S I FOR ATIO Hot Circuit Insertion When circuit boards are inserted into a live backplane, the supply bypass capacitors on the boards draw high peak currents from the backplane power bus as they charge up. The transient currents can permanently damage the connector pins and glitch the system supply, causing other boards in the system to reset. The chip is designed to turn on a board’s supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The chip also provides undervoltage and overcurrent protection while a power good output signal indicates when the output supply voltage is ready. Power-Up Sequence The power supply on a board is controlled by placing an external N-channel pass transistor (Q1) in the power path (Figure 5). Resistor RS provides current detection and capacitor C1 provides control of the GATE slew rate. Resistor R6 provides current control loop compensation while R5 prevents high frequency oscillations in Q1. Resistors R1 and R2 provide undervoltage sensing. After the power pins first make contact, transistor Q1 is turned off. If the voltage at the ON pin exceeds the turn-on threshold voltage, the voltage on the VCC pin exceeds the undervoltage lockout threshold, and the voltage on the TIMER pin is less than 1.233V, transistor Q1 will be turned on (Figure 6). The voltage at the GATE pin rises with a slope equal to 10ᄉ A/C1 and the supply inrush current is set at IINRUSH = CL • 10ᄉ A/C1. If the voltage across the current sense resistor RS gets too high, the inrush current will then be limited by the internal current limit circuitry which adjusts the voltage on the GATE pin to maintain a constant voltage across the sense resistor. Once the voltage at the output has reached its final value, as sensed by resistors R3 and R4, the PWRGD pin goes high. 164112fc 9 LT1641-1/LT1641-2 APPLICATIO S I FOR ATIO RS 0.025 VIN 24V Q1 IRF530 SHORT PIN D1 CMPZ 5248B R5 10 5% R1 49.9k 1% VOUT CL R3 59k 1% C1 R6, 10nF 1k, 5% 8 VCC 7 6 SENSE GATE 1 R7 24k 5% FB ON 2 R4 3.57k 1% LT1641-1 R2 3.4k 1% PWRGD TIMER 3 PWRGD GND 5 GND + 4 C2 0.68ᄉ F 1641-1 F05 Figure 5. Typical Application Short-Circuit Protection The chip features a programmable foldback current limit with an electronic circuit breaker that protects against short-circuits or excessive supply currents. The current limit is set by placing a sense resistor between VCC (Pin 8) and SENSE (Pin 7). To prevent excessive power dissipation in the pass transistor and to prevent voltage spikes on the input supply during short-circuit conditions at the output, the current folds back as a function of the output voltage, which is sensed at the FB pin (Figure 7). When the voltage at the FB pin is 0V, the current limit circuit drives the GATE pin to force a constant 12mV drop across the sense resistor. As the output voltage at the FB pin increases, the voltage across the sense resistor increases until the FB pin reaches 0.5V, at which point the voltage across the sense resistor is held constant at 47mV. The maximum current limit is calculated as: ILIMIT = 47mV/RSENSE For a 0.025 sense resistor, the current limit is set at 1.88A and folds back to 480mA when the output is shorted to ground. 1 Figure 6. Power-Up Waveforms The IC also features a variable overcurrent response time. The time required to regulate Q1’s drain current depends on: Q1’s input capacitance; gate capacitor C1 and compensation resistor R6; and the internal delay from the SENSE to the GATE pin. Figure 8 shows the delay from a voltage step at the SENSE pin until the GATE voltage starts falling, as a function of overdrive. TIMER The TIMER pin (Pin 5) provides a method for programming the maximum time the chip is allowed to operate in current limit. When the current limit circuitry is not active, the TIMER pin is pulled to GND by a 3 ᄉ A current source. After the current limit circuit becomes active, an 80 ᄉ A pull- up current source is connected to the TIMER pin and the voltage will rise with a slope equal to 77ᄉ A/CTIMER as long as the current limit circuit remains active. Once the desired maximum current limit time is set, the capacitor value is: C(nF) = 62 • t(ms). If the current limit circuit turns off, the TIMER pin will be discharged to GND by the 3ᄉ A current source. Whenever the TIMER pin reaches 1.233V, either the internal fault latch is set (LT1641-1) or the autorestart latch is set (LT1641-2). The GATE pin is immediately pulled to GND and the TIMER pin is pulled back to GND by the 3ᄉ A LT1641-1/LT1641-2 164112fc 1 LT1641-1/LT1641-2 APPLICATIO S I FOR ATIO VCC – VSENSE PROPAGATION DELAY 12ᄉ s 47mV 10ᄉ s 8ᄉ s 6ᄉ s 12mV 0V 0.5V VFB 4ᄉ s 50mV 100mV 150mV 200mV 1641-1 F07 Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage current source. When the TIMER pin falls below 0.5V, the GATE pin either turns on automatically (LT1641-2) or once the ON pin is pulsed low to reset the internal fault latch (LT1641-1). The waveform in Figure 9 shows how the output latches off following a short-circuit. The drop across the sense resistor is held at 12mV as the timer ramps up. Since the output did not rise bringing FB above 0.5V, the circuit latches off. For Figure 9, CT = 100nF. Undervoltage and Overvoltage Detection The ON pin can be used to detect an undervoltage condition at the power supply input. The ON pin is internally connected to an analog comparator with 80mV of hysteresis. If the ON pin falls below its threshold voltage (1.233V), the GATE pin is pulled low and is held low until ON is high again. Figure 10 shows an overvoltage detection circuit. When the input voltage exceeds the Zener diode’s breakdown voltage, D2 turns on and starts to pull the TIMER pin high. After the TIMER pin is pulled higher than 1.233V, the fault latch is set and the GATE pin is pulled to GND immediately, turning off transistor Q1. The waveforms are shown in Figure 11. Operation is restored either by interrupting power or by pulsing ON low. 1 VCC – VSENSE 1641-1 F08 2ᄉ s Figure 8. Response Time to Overcurrent Power Good Detection The chip includes a comparator for monitoring the output voltage. The noninverting input (FB pin) is compared against an internal 1.233V precision reference and exhibits 80mV hysteresis. The comparator’s output (PWRGD pin) is an open collector capable of operating from a pullup as high as 100V. The PWRGD pin can be used to directly enable/disable a power module with an active high enable input. Figure 12 shows how to use the PWRGD pin to control an active low enable input power module. Signal inversion is accom- plished by transistor Q2 and R7. Supply Transient Protection The IC is 100% tested and guaranteed to be safe from damage with supply voltages up to 100V. However, spikes above 100V may damage the part. During a short-circuit condition, the large change in currents flowing through the power supply traces can cause inductive voltage spikes which could exceed 100V. To minimize the spikes, the power trace parasitic inductance should be minimized by using wider traces or heavier trace plating and a 0.1ᄉ F bypass capacitor placed between VCC and GND. A surge suppressor at the input can also prevent damage from voltage surges. 164112fc LT1641-1/LT1641-2 APPLICATIO S I FOR ATIO RS 0.025 VIN 24V SHORT PIN R1 49.9k 1% Q1 IRF530 D1 CMPZ 5248B R5 10 5% 8 V CC 7 CL R3 59k 1% R7 24k 5% 6 SENSE GATE 1 FB ON 2 R4 3.57k 1% LT1641-1 R2 3.4k 1% PWRGD TIMER 3 PWRGD GND 5 Figure 9. Short-Circuit Waveforms V OUT C1 R6, 10nF 1k, 5% D2 30V 1N5256B GND + 4 C2 0.68ᄉ F 1641-1 F10 Figure 10. Overvoltage Detection Figure 11. Overvoltage Waveforms GATE Pin Voltage A curve of gate drive vs VCC is shown in Figure 13. The GATE pin is clamped to a maximum voltage of 18V above the input voltage. At minimum input supply voltage of 9V, the minimum gate drive voltage is 4.5V. When the input supply voltage is higher than 20V, the gate drive voltage is at least 10V and a regular N-FET can be used. In applications over a 9V to 24V range, a logic level N-FET must be used with a proper protection Zener diode between its gate and source (as D1 shown is Figure 5). 164112fc LT1641-1/LT1641-2 APPLICATIO S I FOR ATIO Layout Considerations high current applications. To improve noise immunity, put the resistor divider to the ON pin close to the chip and keep traces to VCC and GND short. A 0.1ᄉ F capacitor from the ON pin to GND also helps reject induced noise. Figure 14 shows a layout that addresses these issues. To achieve accurate current sensing, a Kelvin connection is recommended. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 530ᄉ / . Small resistances add up quickly in RS 0.01 VIN 48V Q1 IRF530 SHORT PIN R1 294k 1% R6, 1k, 5% 8 V CC UV = 37V D1 CMPZ 5248B R5 10 5% 7 6 SENSE GATE R3 143k 1% ACTIVE LOW ENABLE MODULE C1 10nF + R7 47k 5% 1 VIN + CL 220ᄉ F FB PWRGD TIMER GND 5 4 V OUT – R4 4.22k 1% LT1641-1 R2 10.2k 1% V OUT ON/OFF VIN – 2 ON V OUT + 3 Q2 MMBT5551LT1 C2 0.68ᄉ F GND 1641-1 F12 Figure 12. Active Low Enable Module 18 ILOAD 16 SENSE RESISTOR, RS R1 8 LT1641-1 GND 10 SENSE V CC 12 ON VGATE – VCC (V) 14 6 4 R2 2 0 8 13 18 VCC (V) 23 ILOAD 1641-1 F13 Figure 13. Gate Drive vs Supply Voltage 10 1641-1 F14 Figure 14. Recommended Layout for R1, R2 and RS 164112fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- 11 LT1641-1/LT1641-2 tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. LT1641-1/LT1641-2 PACKAGE DESCRIPTIO S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 NOTE 3 .050 BSC 8 7 6 5 .160 ᄆ .005 MIN .150 – .157 (3.810 – 3.988) NOTE 3 .228 – .244 (5.791 – 6.197) .030 ᄆ .005 TYP 1 2 3 4 RECOMMENDED SOLDER PAD LAYOUT .010 – .020 ᅲ 45ᄚ (0.254 – 0.508) .008 – .010 (0.203 – 0.254) .053 – .069 (1.346 – 1.752) 0ᄚ – 8ᄚ TYP .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN .004 – .010 (0.101 – 0.254) .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) .050 (1.270) BSC SO8 0303 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1640A Negative High Voltage Hot Swap Controller Controls an N-FET at Negative Side to – 80V LTC1421 Dual Channel Hot Swap Controller Operates Two Supplies from 3V to 12V and a Third to – 12V LTC1422 High Side Drive Hot Swap Controller in SO-8 System Reset Output with Programmable Delay LTC1643 PCI Hot Swap Controller 3.3V, 5V, 12V, – 12V Supplies for PCI Bus LTC1642 Fault Protected Hot Swap Controller Operates from 3V to 16.5V, Handles Surges to 33V LT4250 Negative 48V Hot Swap Controller Active Current Limiting for Supplies from – 20V to – 80V 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 LT1641-1/LT1641-2 164112fc (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LT/LWI 0706 REV C ユ PRINTED IN USA ᄅ LINEAR TECHNOLOGY CORPORATION 2001