Download Electronics II Lecture 3(b): Transistor Bias Circuits

Electronics II
Lecture 3(b): Transistor Bias Circuits
A/Lectr. Khalid Shakir
Dept. Of Electrical Engineering
College of Engineering
Maysan University
Electronic Devices, 9th edition
Thomas L. Floyd
Copyright @2013 by Dept. of Electrical Engineering,
College of Engineering, Maysan University
1-11
© 2012 Pearson Education. Upper Saddle River, NJ, 07458.
All rights reserved.
Electronics II- Lecture 3(b)/1st Semester 013/014
Linear Operation
Bias establishes the operating point (Q-point) of a transistor
amplifier; the ac signal
I (mA)
moves above and below
Load line
this point.
C
For this example, the dc base
current is 300 A. When the
input causes the base current
to vary between
200 A and 400 A, the
collector current varies
between 20 mA and 40 mA.
Electronic Devices, 9th edition
Thomas L. Floyd
Copyright @2013 by Dept. of Electrical Engineering,
College of Engineering, Maysan University
Ic
40
ICQ
Ib
A
Q
0
400 µ A
40
30 µ A= I
300
B
20
BQ
200
20 µ A
0
1.2
3.4
VCEQ
VCE (V)
5 .6
Vce
2-11
© 2012 Pearson Education. Upper Saddle River, NJ, 07458.
All rights reserved.
Electronics II- Lecture 3(b)/1st Semester 013/014
Waveform Distortion
A signal that swings
outside the active
region will be clipped.
For example, the bias
has established a low Qpoint.
IC
Input
signal
ICQ
As a result, the signal
will be clipped because
it is too close to cutoff.
Q
Cuto f
VCC
0
VCE
Cuto f
Vce
VCEQ
Electronic Devices, 9th edition
Thomas L. Floyd
Copyright @2013 by Dept. of Electrical Engineering,
College of Engineering, Maysan University
3-11
© 2012 Pearson Education. Upper Saddle River, NJ, 07458.
All rights reserved.
Electronics II- Lecture 3(b)/1st Semester 013/014
Waveform Distortion
High Q- point. The signal will be
clipped because it is too close to
saturation.
Electronic Devices, 9th edition
Thomas L. Floyd
Copyright @2013 by Dept. of Electrical Engineering,
College of Engineering, Maysan University
Input signal too large. The signal
will be clipped from both sides.
4-11
© 2012 Pearson Education. Upper Saddle River, NJ, 07458.
All rights reserved.
Electronics II- Lecture 3(b)/1st Semester 013/014
Q. A signal that swings outside the active area will be
a. clamped
b. clipped
c. unstable
d. all of the above
Electronic Devices, 9th edition
Copyright
@2013 by Dept. of Electrical Engineering,
Thomas L. Floyd
College of Engineering, Maysan University
5-11
© 2012 Pearson Education. Upper Saddle River, NJ, 07458.
All rightsElectronics
reserved.
II- Lecture 3(b)/1st Semester 013/014
Voltage-Divider Bias
A practical way to establish a Q-point is to form a voltagedivider from VCC.
R1 and R2 are selected to establish VB. If the
divider is stiff, IB is small compared to I2. Then,
+VCC
RC
I2
R2
Copyright @2013 by Dept. of Electrical Engineering,
College of Engineering, Maysan University
6-11
RE
© 2012 Pearson Education. Upper Saddle River, NJ, 07458.
All rights reserved.
Electronics II- Lecture 3(b)/1st Semester 013/014
Q. A stiff voltage divider is one in which
a. there is no load current
b. divider current is small compared to load current
c. the load is connected directly to the source voltage
d. loading effects can be ignored
© 2012 Pearson Education. Upper Saddle River, NJ, 07458.
Copyright @2013 by Dept. of Electrical Engineering,
College of Engineering, Maysan University
7-11
Electronics II- Lecture 3(b)/1st Semester 013/014
Voltage-Divider Bias
+VCC
+15 V
R1
27 k
βDC = 200
Determine the base voltage for the circuit.
 R2 
V CC
VB  
R1  R2 

12k 
 
 15V   4.62 V

 27 k  12 k 
RC
1.2 k
R2
12 k
RE
680 
© 2012 Pearson Education. Upper Saddle River, NJ, 07458.
Copyright @2013 by Dept. of Electrical Engineering,
College of Engineering, Maysan University
8-11
Electronics II- Lecture 3(b)/1st Semester 013/014
Voltage-Divider Bias
+VCC
+15 V
What is the emitter voltage, VE, and current, IE?
R1
27 k
VE is one diode drop less than VB:
4.62 V
VE = 4.62 V – 0.7 V = 3.92 V
RC
1.2 k
βDC = 200
3.92 V
Applying Ohm’s law:
R2
12 k
RE
680 
VE 3.92V
IE 

 5.76 mA
RE 680 
© 2012 Pearson Education. Upper Saddle River, NJ, 07458.
Copyright @2013 by Dept. of Electrical Engineering,
College of Engineering, Maysan University
9-11
Electronics II- Lecture 3(b)/1st Semester 013/014
Q. Assuming a stiff voltage-divider for the circuit shown,
the emitter voltage is
+VCC
+15 V
a. 4.3 V
R1
20 k
b. 5.7 V
RC
1.8 k
βDC = 200
c. 6.8 V
d. 9.3 V
R2
10 k
RE
1.2 k
VB = 10 / (10 + 20) * 15 = 5 V
VE = 5 – 0.7 = 4.3 V
Electronic Devices, 9th edition
Thomas
L. Floyd
Copyright
@2013 by Dept. of
Electrical Engineering,
College of Engineering, Maysan University
10-11
© 2012 Pearson Education. Upper Saddle River, NJ, 07458.
All rights reserved.
st
Electronics II- Lecture 3(b)/1 Semester 013/014
Q. For the circuit shown, the dc load line will intersect the
y-axis at (neglecting IB)
+VCC
+15 V
a. 5.0 mA
R1
20 k
b. 10.0 mA
RC
1.8 k
βDC = 200
c. 15.0 mA
d. none of the above
R2
10 k
RE
1.2 k
@ VCE=0:
IC = (15 – 0) / (1.8k + 1.2k) = 15 / 3k = 5 mA
Copyright @2013 by Dept. of Electrical Engineering,
College of Engineering, Maysan University
11-11
© 2012 Pearson Education. Upper Saddle River, NJ, 07458.
All rights reserved.
Electronics II- Lecture 3(b)/1st Semester 013/014