Download The ”digital” ADC

The ”digital” ADC
The nanometer technology analog-to-digital converter.
Goal:
Make a scalable analog-to-digital converter for digital technology generated from essential
performance parameters (SQNR, power, clockrate).
Advisors:
Tor Sverre Lande
Dag Trygve Wisland
Keywords: Layout generator, analog-to-digital conversion, noise-shaping, oversampled
converters, VCOs
Background
The frequency-modulated frequency-to-digital converter (FDSM) may cope with technology
scaling and lower supply voltages of state-of-the-art digital technology and to a minor extend is
suffering of the SQNR-squeezing known from traditional AM modulated systems mostly used
today. These results are based on the pioneering work of Mats Høvin followed up by Dag
Wisland, both former Ph.D. students at Dept. of Informatics, Univ. of Oslo.
The FDSM concept is also scalable in performance. Either by increasing gate count or by
cranking up the oversampling ratio (OSR), SQNR may be improved by the cost of increased
power. The non-feedback architecture combined with parallel converter structures enables these
trade-offs.
There are two main reasons why these converters are superior to traditional approaches in
advanced technologies:
1. By coding the analog state as an FM signal, the SNR of the variable is independent of the
power supply. The analog state has been converted from an amplitude voltage to timedomain continuous frequency variation. It is important to notice that an FM coded state is
still analog. Given an FM coded state, the FM-to-digital is surprisingly modular and
simple.
2. The conversion problem has been “shifted” to FM coding of an analog state. This is far
from simple since the conversion quality is directly a function of the SNR of the FM
encoding. There are a number of VCOs suitable for this encoding and basically anyone
would do with whatever SNR and linearity available for a given modulation. Fine-pitch
microelectronics is known to “suffer” from short-channel effects making even saturated
devices linear reducing digital performance. For VCOs this “degradation” may be an
advantage increasing linearity and dynamic range!
The FDSM concept
FDSM (or Frequency-to-Delta-Sigma-Modulator) is well documented, both theoretical and in
practical silicon. The awarded ESSCIRC paper “A Novel Multi-Bit Parallel .Ó FM-to-Digital
Converter with 24-bit Resolution” clearly demonstrates with measurements the scalability up to
24-bit dynamic range. The fundamental theory was established in Høvin’s Ph.D thesis and earlier
work also reported in JSSC: M. Høvin, A. Olsen, T.S. Lande and C. Toumazou, “Delta- Sigma Modulators
Using Frequency-Modulated Intermediate Values”, IEEE Journal of Solid-State Circuits, vol. 32, no. 1, pp. 13–22,
January, 1997.
Here we will just show the concept and the basic equations in the context of an ADC.
Figure 1 Fundamental FDSM-based ADC
The simplest possible ADC is shown in figure Figure 1 and is remarkably simple. A VCO made
as a ring-oscillator modulating frequency with power rails do the frequency encoding. The FDSM
is simply made by to D-latches and one XOR-gate (adder). The decimator is not shown here since
this is required in any oversampled system.
Figure 2 Parallel architecture
It is both advisable and convenient to add one FDSM converter to each internal node of the ringoscillator as shown in Figure 2. SQNR is increased by 3dB for each doubling of parallel
converters (provided quantization noise is uncorrelated). More important is the dithering achieved
due to transistor variations. Each FDSM converter is a 1. order sigma-delta converter with all the
familiar problems with tones. The traditional way of reducing this problem is to add minor noise.
Here we achieve the same affect by exploring transistor mismatch.
Formally the FDSM performance may be approximated by:
  2  2 f 3 

f 
  10 log   bw  
SQNR  20 log  m 2
 36  f S  
fS 



with
m – number of parallel converters
f – modulation index
fs – Sampling frequency
fbw – max signal frequency
From this equation it is possible to make a program (SKILL code) for generating a suitable
FDSM giving the required performance trading clock, power, area….
It is all digital and scales well with technology.
The FM encoder
The analog “problems” have been pushed to the encoding of the analog state as an FM coded
variable. There are several ways to do this, but in the end, the quality of this encoding determines
the overall performance. The most crucial parameter is the noise performance. Also linearity is
important, but some non-linearity may be shaped up in the decimator. Often VCO frequency
characteristics have a sigmoid shape which is stable and could be shaped up in the digital filter.
The most “digital” VCO is the familiar ring-oscillator. The simplest tuning scheme is to modulate
the power rail(s) with the analog input. Traditionally this scheme is know to give poor linearity,
but here technology is working in our favor. Fine-pitch devices are “degrading” to linear devices
which is perfect for ring-oscillators! We should be able to explore short-channel effects to make
linear ring-oscillators. The simple ring-oscillator is able to run at pretty high frequencies (carrier)
combine with improved linearity of fine-pitch devices, we should have the most digital ADC you
can think of: Only one pure analog node (power rail of the ring). Only familiar digital parts in the
rest of the circuit (inverters, D-latches, XOR gates and adders).
Provided ring-oscillators are meeting our specs, we should be able to automate also this part of
the converter as well.
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Master projects
1. FDSM layout generator
Based on insight in the FDSM concept a layout generator implemented in a suitable
script/programming language (SKILL?) is going to be designed. Based on reported performance,
important parameters should be tunable by the user:
 Bandwidth
 Carrier frequency
 Modulation index
 Signal-to-Quantization-noise-ratio (SQNR)
 Clock-rate
If feasible the layout generator should generate a layout meeting these specifications with a given
estimated power consumption. The solution should be prepared for easy transfer to different
technologies. A test-chip should be made verifying the solution.
2. VCOs in fine-pitch technology
As a front end to the FDSM a suitable voltage controlled oscillator/FM encoder should be
implemented as a layout code generator. The VCO should be implemented as a ring-oscillator
exploring fine-pitch technology. Different ring-oscillator structures should be studied
(differential, single-ended…) and important properties like linearity and phase noise should be
studied. The VCO-generator should take parameters like:
 Number of taps
 Linearity
 Modulation index
The generator should give estimates of expected phase noise and linearity for the generated
layout. The generator should be designed for easy porting to another technology. The work
should be verified through measurement of real silicon.