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ECE 15B Computer Organization
Spring 2010
Dmitri Strukov
Lecture 2: Overview of Computer Organization
Partially adapted from Computer Organization and Design, 4th edition, Patterson and Hennessy, and classes taught by
Patterson at Berkeley, Ryan Kastner at UCSB and Mary Jane Irwin at Penn State
“Von-Neumann” Computer
Store –programmed concept
was not invented by John von
Neumann only
Other inventors Presper Eckert
and John Mauchly ENIAC 1943
University of Pensilvania
Computer
Processor
Control
Datapath
Memory
(where
programs,
data
live when
running)
Devices
Input
Output
ECE 15B Spring 2010
Keyboard,
Mouse
Disk
(where
programs,
data
live when
not running)
Display,
Printer
Layers of Abstraction
Application (ex: browser)
Compiler
Software
Hardware
Assembler
Processor
This class is about
this region
Operating
System
(Mac OSX)
Memory I/O system
Instruction Set
Architecture
Datapath & Control
Digital Design
Circuit Design
transistors
Need Many Layers to Handle Complexity
ECE 15B Spring 2010
Below the Program
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
High Level Language
Program (e.g., C)
Compiler
Assembly Language
Program (e.g.,MIPS)
Assembler
Machine Language
Program (MIPS)
Machine
Interpretation
lw
lw
sw
sw
0000
1010
1100
0101
Hardware Architecture Description (e.g.,
block diagrams)
Architecture
Implementation
Logic Circuit Description
(Circuit Schematic Diagrams)
$t0, 0($2)
$t1, 4($2)
$t1, 0($2)
$t0, 4($2)
1001
1111
0110
1000
1100
0101
1010
0000
0110
1000
1111
1001
1010
0000
0101
1100
1111
1001
1000
0110
0101
1100
0000
1010
1000
0110
1001
1111
Review: Unsigned Binary Representation
Hex
Binary
Decimal
0x00000000
0x00000001
0x00000002
0x00000003
0x00000004
0x00000005
0x00000006
0x00000007
0x00000008
0x00000009
0…0000
0…0001
0…0010
0…0011
0…0100
0…0101
0…0110
0…0111
0…1000
0…1001
…
1…1100
1…1101
1…1110
1…1111
0
1
2
3
4
5
6
7
8
9
0xFFFFFFFC
0xFFFFFFFD
0xFFFFFFFE
0xFFFFFFFF
231 230 229
...
23 22 21 20
31 30 29
...
3 2 1
1 1 1
...
1 1 1 1 bit
1 0 0 0
...
0 0 0 0 - 1
232 - 1
232 - 4
232 - 3
232 - 2
232 - 1
ECE 15B Spring 2010
0
bit weight
bit position
Data input: Analog  Digital
• Real world is analog!
• To import analog
information, we must do
two things
– Sample
• E.g., for a CD, every
44,100ths of a second, we
ask a music signal how loud
it is.
– Quantize
• For every one of these
samples, we figure out
where, on a 16-bit (65,536
tic-mark) “yardstick”, it
lies.
www.joshuadysart.com/journal/archives/digital_sampling.gif
ECE 15B Spring 2010
Logic Design Basics
• Information encoded in binary
– Low voltage = 0, High voltage = 1
– One wire per bit
– Multi-bit data encoded on multi-wire buses
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Grouping of signals
ECE 15B Spring 2010
Why binary?
Other logic styles allow for
implementations of multilevel logic
(e.g. threshold logic)
CMOS digital design style, which is the
most power efficient and therefore
currently dominating, enforces binary
signal representation
ECE 15B Spring 2010
The lowest layer of hierarchy
ECE 15B Spring 2010
How to build combinational elements?
• AND-gate

–Y=A&B
A
B

Multiplexer

A
+
Y=A+B
B
Y


Adder
Arithmetic/Logic Unit

Y = F(A, B)
Y = S ? I1 : I0
I0
I1
M
u
x
A
ALU
Y
B
F
S
ECE 15B Spring 2010
Y
Y
Gate level design: NAND
N instances of 1-bit wide multiplexor
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1-bit-wide multiplexor
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Implementation of 1-bit-wide
multiplexor
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4-to-1 multiplexor
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Hierarchical construction of MUXes
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Building adder
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Building adder
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Building adder
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Ripple carry adder
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Circuit delay
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Simple ALU
ECE 15B Spring 2010
Combinational logic
• Complex logic blocks are built from basic AND,
OR, NOT building blocks we will see shortly
• A combinational logic block is one in which
the output us a function only of its current
input
• Combination logic cannot have memory
ECE 15B Spring 2010
Sequential logic = Flip Flops +
combination logic
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How to implement?
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Will that work?
ECE 15B Spring 2010
Sequential Elements
• Flip flop: stores data in a circuit
– Uses a clock signal to determine when to update
the stored value
– Edge-triggered: update when Clk changes from 0
to 1
Clk
D
Q
D
Clk
Q
ECE 15B Spring 2010
Sequential Elements
• Flip flop with write control
– Only updates on clock edge when write control
input is 1
– Used when stored value is required later
Clk
D
Write
Clk
Q
Write
D
Q
ECE 15B Spring 2010
Register
ECE 15B Spring 2010
D flip flop gate design
ECE 15B Spring 2010
Second try for previous example
ECE 15B Spring 2010
Clock + sequential logic = synchronous
design
• Clock rate (clock cycles per second in MHz or
GHz) is inverse of clock cycle time (clock period)
CC = 1 / CR
one clock period
10 nsec clock cycle => 100 MHz clock rate
5 nsec clock cycle => 200 MHz clock rate
2 nsec clock cycle => 500 MHz clock rate
1 nsec (10-9) clock cycle => 1 GHz (109) clock rate
500 psec clock cycle => 2 GHz clock rate
250 psec clock cycle => 4 GHz clock rate
200 psec clock cycle => 5 GHz clock rate
ECE 15B Spring 2010
Clocking Methodology
• Combinational logic transforms data during
clock cycles
– Between clock edges
– Input from state elements, output to state
element
– Longest delay determines clock period
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CPU Overview
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… with muxes

Can’t just join wires
together

ECE 15B Spring 2010
Use multiplexers
… with muxes
ECE 15B Spring 2010