Download EC-705put

CORPORATE INSTITITUTE OF SCIENCE & TECHNOLOGY, BHOPAL
Important Questions
VLSI DESIGN (EC-705)
UNIT I
Q1 what do you understand by IC (integrated circuit). Classify the IC in details.
Q2 . Draw the flow chart of conventional IC Design process and explain.
Q3 Explain the CZ (Czocharlaski) method of wafer preparation.
Q4 Explain the term photolithography and describe its various steps in detail.
Q5. Describe the methods of oxidation used in IC fabrication.
Q6. Define microelectronic fields and major processes used in IC fabrication.
Q7. Explain the various steps involved in IC production process in details.
Q8.Explain layout design rules and various process parameters.
Q9.write short notes on:Bipolar technology
Hybrid technology
Q10. Explain the Size and complexity of IC.
UNIT II
Q1. Explain the term Device modeling. Explain the DC and small signal model of a device.
Q2. Explain the MOS DC Model
Q3. Explain the small signal MOSFET Model.
Q4. Explain the High frequency MOSFET Model.
Q5. Explain the MOSFET Noise Source Modeling.
Q6. Explain the large signal MOSFET Model.
Q7. what do you understand by Device Models .Differentiate DC and AC device models.
Q8. Explain the y-parameters and its application for small signal analysis.
Q9. For a two port network the mathematical relationship between variables is given by
equations
V1 = I1 R1
I2 = I0 e K1 V1 + V2 /R2 V1 > 0
I2 = K2 V12 + I0 + V2 /R2 V1 <0
Determine the Dc model of the network
Determine the small signal model of the network for V1 > 0
Determine the small signal model of the network for V1 < 0.
Q10.Using the typical MOS parameter for λ= 3μ m (VT0 = 0.75, K= 24μA/V2, ϕ = 0.6 ,ϒ= .4)
Determine the op voltage for the circuit shown below if R= 15 kΩ.
Determine maximum allowable range of R for device to be in saturation region.
UNIT III
Q1 .Explain the SPICE MODELS and its significance.
Q2. Describe Eber-Molls MODEL for BJT.
Q3. Explain the High Frequency BJT Model.
Q4.Explain the Noise Source Modeling of BJT.
Q5. Write Short Notes on –
(a).Short channel devices (b) Sub threshold operation (c) Passive component Model
Q6.Explain the diode DC Model / Large signal Model.
Q7.Explain Small Signal Model and High Frequency Model.
Q8. Explain the BJT DC Model or Large Signal Model.
Q9. Explain the small Signal BJT Model.
Q10. Write Short notes on:
(a)MOS Level 1 large signal Model
(b)MOS Level 2 large signal Model
(c) Temp dependency of BJT.
UNIT IV
Q1. Explain the term random logic and structured logic form.
Q2. Explain the static Register cell and quasi- static register cell.
Q3. Describe the bit serial processing elements in detail.
Q4. Write short notes on
(a)Systolic array
Q5. Explain the Algotronix architecture
Q6. What do you understand by logic structures? Classify the logic structures.
Q7. Describe the register storage circuit with diagram.
Q8. Explain the architecture of Micro coded controllers.
Q9. What are the steps and procedure of microprocessor designing?
Q10.Explain the architecture of algotronix.
UNIT V
Q1.Explain the Pwell process of CMOS fabrication.
Q2 Design the Layout of 2 input NAND Gate.
Q3 Explain the LAMBDA (λ) and µ Rules of layout out Design.
Q4 Describe the twin tub process of CMOS fabrication.
Q5 Define latch up and gives its disadvantage .
Q6. Explain NMOS transistor fabrication process with diagrams.
Q7. What are the various methods of CMOS fabrication process?
Q8. Describe any one method in details.
Q9. Define Latch-up. Explain various triggering methods of latch up and how can it be
prevented?
Q10. Write short notes on interconnects and circuit elements in VLSI circuits.