Download interim report on final year project

INTERIM REPORT ON FINAL YEAR PROJECT
Incremental Algorithms for Circuit Partitioning in VLSI
Physical Design Automation.
Instructor: Prof. Prosenjit Gupta
1. PROBLEM STATEMENT
The circuit layout problem is subdivided into a collection of subproblems. Circuit partitioning is a step in VLSI physical design to divide
the circuit into sub-circuits. With millions of transistors on a single chip,
it is not feasible to layout the entire chip in a single step.
During partitioning, the design is partitioned into sub circuits (blocks)
and the output is a set of blocks and interconnections between them.
Other advantages of circuit partitioning include:
system level partitioning for multi chip design, circuit simulation
and parallel cad development.
For present generation VLSI chips, to deal with their inherent complexity,
incremental algorithms are needed when the design undergoes local or
incremental change.
Incremental partition
Incremental algorithm for synthesis and layout are needed where design
undergoes local or incremental change. The main challenge is to decide
which instances we need to apply these algorithms and what are the
quality/speed tradeoffs.
 An original (hyper) graph and its near-optimal partitioning
results are given.
 An incrementally changed (hyper)graph is obtained by
adding/deleting vertices/edges from the original graph.
 Incremental partitioning problem is to find the near optimal
partitioning for the changed (hyper)graph without doing from the
scratch.
 Incremental partitioning should be much faster than the
original partitioning.
 It is preferable to use the existing partitioning results for
the original (hyper)graph
2. BACKGROUND
Circuit partitioning divides a given circuit into a collection of smaller
sub-circuits to minimize the number of connections among the subcircuits, subject to the area balance constraint. The circuit partitioning
problem becomes more important as VLSI technology reaches submicron device dimensions. Traditionally, this problem was important for
breaking up a complex system into several custom ASICs.
Though it is possible to solve the case of unbounded partition sizes
exactly, the case of balanced partition sizes is NP complete.
Kernighan and Lin have shown that in the worst case , it will take
exponential time to divide a set of circuit elements into k blocks by
enumerating all possible permutation in which n circuit components can
be divided into k equal blocks of size p = n/k.
total number of unique way of partitioning the graph is
N(k) = 1/K! (n p) (n-p p) (n-2p p) .... (p p) = n!/[k! (p!)^k]
1/k! because it includes all K! permutation
N(k) = O( (n/p)^ ( (n-p)/p)) Sterling’s approximation
It is NP – complete problem shown by KARPK.
Partitioning problem can be solved by following techniques:1.
2.
3.
4.
5.
Clustering
Graph
Ratio cut
Stochastic algorithms.
Neural network.
The particular bi-partitioning problem can be defined as follows:
Let us assume a hypergraph H=(V,E), with n=|V| nodes and m=|E|
edges. The goal is to find such a partition (V1,V2) of V that minimizes the
number of hyperedges that have nodes in different set (V1, V2) under the
defined constraint of the partition size. It can be also expressed by the
balance/unbalance of the partition size. The set of external hyperedges
can be labeled as Ecut (V1,V2) and the following cost function is defined.
Over the years many algorithms for solving the problem “circuit
partitioning “ have been developed. Depending on the basic ideas of these
algorithms several different classifications can be undertaken. One is the
differentiation between constructive and iterative algorithms.
1. Constructive algorithms start with empty partitions and fill these
partitions with elements during a run. An example are the
algorithms presented by Kodres which start from one (or more)
seed elements to form partitions. The solution quality of such a
clustering algorithm is in most cases highly dependent on the
initial choice of the seed element.
2. Iterative techniques start with an initial random solution and try
to improve this solution in one or more sequential runs. The first
algorithm of this kind has been introduced by Kernighan and Lin
and is specialized in bipartitioning. This algorithm tries to improve
an initial solution by swapping the partition assignment of two
elements. The algorithm has been improved later by Fiduccia.
3. Kernighan and Lin (Kris) in 1970 proposed a two-way graph
partitioning algorithm which became the basis for most of the
subsequent partitioning algorithms. The KL algorithm operates
only on balanced partitions and performs a number of passes over
the cells of the circuit where each pass comprises a repeated
operation of pairwise cell swapping for all pairs of cells.
4. Fiduccia and Mattheyses (FM) in 1982 obtained a faster
implementation of KL with the help of a new data structure, called
the bucket data structure. FM can operate on unbalanced
partitions and employs a single cell move instead of a swap of a cell
pair at each step in a pass.
CM Fiduccia and RM mthyeses algorithms gave a linear- Time
heuristic for improving network partition.
FM method runs in O(n log n ) time .By use of specialized data
structures (bucket arrays) a single iteration of the algorithm has
the complexity of O(n) instead of O(n log n) in the KL-algorithm.
5. Krishnamurthy [KM] in 1984 enhanced the FM-algorithm with a
look-ahead strategy using level gains . Krishnamurthy refined the
technique of choosing the best cell for the movement to the other
block by adding a look-ahead (LA) mechanism. Krishnamurthy's
algorithm maintains a multi-dimension version of the FM data
structures, which lists expected gains of cells in future moves.
6. Dutta and Deng recently proposed a new probability based
augmentation of the graph partitioning algorithm called the
probabilistic gain computation approach which is capable of
capturing the global and future implication of a moving a node at
the current time.
7. Sanchis [sanchis] generalized these approaches to k-way
partitioning. Sanchis generalized Krishnamurthy's algorithm to a
multiway circuit partitioning algorithm so that it could handle the
partitioning of a circuit into more than two parts. It should be
noted that all the previous approaches before Sanchis' algorithm
(FMS algorithm) are originally bipartitioning algorithms.
Sanchis approach takes about O(LkP*log(k+p+L))time. P= total
number of connections, p = no of pins, L= no of level for k=2 L=1
this time reduced to linear as shown by F-M
3. PLAN
Following are the features to be implemented as a part of
Incremental partitioning:Implementation of basic partitioning algorithm
K-L and FM algorithms in the view of following aspects
-Changing constraint on circuit.
-Changing balance criteria on circuit.
- Testing on different circuit benchmark.
 Designing of incremental algorithm for circuit partition, depending
on increase and decrease in circuit element, including dynamic
criteria of partitioning.
 Implementation of incremental partitioning of a circuit.
4. IMPLEMENTATION
1. A possible implementation of the circuit portioning as a KernighanLin algorithm and FM algorithm.
2. Implementation of incremental partitioning.
KL-algorithm:
Pair-wise exchange of nodes to reduce cut size
Allow cut size to increase temporarily within a pass
Compute the gain of a swap
Repeat
Perform a feasible swap of max gain
Mark swapped nodes .locked.;
update swap gains;
Until no feasible swap;
Find max prefix partial sum in gain sequence g1, g2, .,gm
Make corresponding swaps permanent.
Start another pass if current pass reduces the cut size
(usually converge after a few passes)
 K-L runs in O(n^2 logn ) time
FM- algorithm:
1. Start with "balance" partition
2. Move across partition if move does not violate balance condition
3. To choose next vertex
a. find max gain vertex max.
b. move vertex if balanced condition is not violated
c. lock vertex .
4. identify the critical nets and update gain of only those cell that are
connected by those nets.
Incremental algorithm:
For the given graph H , incrementally changed graph H’ is only partially
different than H, so we can think of partitioning solution on H is similar
to partitioning solution on H’. The difference in solutions of H and H’
could be just the vertices in N diff and vertices close to them.
Define value of topological proximity for each vertex in H’.
Assign 0 proximity to vertices in N diff and vertices corresponded to all
the hyperedges in N diff. (N diff are those vertices where we are making
the changes)
Assign 1 to those who are directly connected to 0 value proximity
vertices.
Similarly for k – value .
Apply breadth first search to find the proximity values.
Higher proximity values vertices are fixed and those lower than the
threshold value vertices can move actively.
Now find the partitioning solution for H’ for the threshold values vertices.
5. Timeline
 Studying – till November (current works)
 Implementation of basic partitioning algorithm– 2nd week of
January
 Research work – 1st week of February
 Implementation of incremental – by February end
 Testing - 1st week of march
 Final Demonstration – 2nd Week of March
Project Members:
Arjun Kumar[200101015]
Vinod Gupta [200101096]