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Motivation
speed (bps)
Emerging applications of optical communications
requiring higher integration and lower power:
Long-haul
Optic-fiber
1T
1G
Optical LAN
Optical
Interconnect
FTTH
ATM-PON
IR Wireless
1M
0.1
1
10
100
1k
distance (m)
© 2001 IEEE International Solid-State Circuits Conference
10k
© 2001 IEEE
100k
Objective
To develop a 1V optical preamp in conventional CMOS
Rf 3
+
Vbias
1
!
-
Vout
2
Design Challenges
1. Maximizing photodiode bias voltage
2. Wide output signal swing
3. Achieving variable-gain for wider dynamic-range
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Conventional TIA Topologies
Two-stage
VDD
VDD , min > 2V GS ≈ 1.6V
+
VGS
"
-
+
VGS
-
Unsuitable for 1V operation
Single-stage
1V
1V
+
~0.8 V
~0.2 V
+
VGS
# Capable of 1V operation
# Large output swing, Vt=0.6V
" Small PD bias voltage ~ 0.2V
-
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Proposed Low-Voltage TIA
LV current amplifier in transimpedance configuration
1V
1V
I B1
VDGB
(~1.7V)
1V
~0.8V
+
~0.8V
-
M1
Vb1
(~0.9V)
~0.2V
IB2
v out
Rf
M2
~0.8V
M3
# 1V operation
# Large output swing, Vt=0.6V
# Large PD bias, VDD – VDSsat2 ~0.8V
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Design Optimization
Bandwidth
g (1 + A –1 )
m1
I
ω – 3dB = --------------------------------------------------------------------------C
+C
+g R C ⁄ A
gs1
db2
m1 f out
I
Gain
AI
v out
---------- = --------------- ( 1 ⁄ g – R )
m1
f
iP D
1 + AI
g m3
A I = ---------g m2
Gain ×Bandwidth (GHz Ω)
500
Optimum point [50MHz]
(5kΩ,12dB)
400
300
*
200
100
0
15
10
5
R (kΩ)
f
© 2001 IEEE International Solid-State Circuits Conference
0 -20
20
0
Current gain, A (dB)
I
© 2001 IEEE
Achieving Variable Gain
!
Gate voltage of NMOS resistor must be biased higher than
the 1V supply
!
Solution: Use voltage doubler to directly bias the gate
Dynamic Gate Biasing
IB
0.8V
1V 1V
i=0
2x
1.6V
0.8V
0.8V
#Charge pump supplies no current, minimizing ripple
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Sub-1V Bias VoltageDoubler
!
Uses full supply swing for driving switches
!
A separate input for the bias voltage
!
Capable of doubling voltages near the device threshold
1.7V
0.7V
Vin=0.85V
Φ1
Φ2
0.7V
Φ1Vin
Φ2Vin
Φ 1Vin
Φ1
Φ1
Φ2
Φ2
Φ 2Vin
Basic charge pump
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
1V
V in
Chip Block Diagram
Optical Front-End IC
10kHz
Clock
Vin
Vin+
Vin-
VDGB
Charge
Pump
Preamp
Post Amp #1
Test
transconductor
CL
Post Amp
#2
Analog
MUX
TestIn
Output
Buffer
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
50 Ω
Out+
Out50 Ω
Test
transconductor
Output
Analog MUX Buffer
Post 2
Post 1
Preamp
Limiter
Bias
Bias
4x1
Decoder
Output
Driver
Bias Voltage
Doubler
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Transimpedance gain(kOhms)
Experimental Frequency Response
Preamp + Post Amp #1 & #2
100
50MHz
Preamp + Post Amp #1
10
Preamp only
1
1
10
frequency(MHz)
© 2001 IEEE International Solid-State Circuits Conference
45MHz
100
© 2001 IEEE
Input-referred noise current (pA/Hz0.5)
Input Noise Spectrum
30
25
20
15
11 pA/Hz1/2
10
5
0
1
10
frequency (MHz)
100
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Eye Diagram
75 Mb/sec free-space optical link
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Controlling Charge Injection
Eye
Diagram
Doubler
Clock
No external capacitor
(10 pF on chip)
© 2001 IEEE International Solid-State Circuits Conference
With 200pF
external capacitor
© 2001 IEEE
Performance Summary
Technology
Supply voltage
Power dissipation
Photodiode capacitance
0.35 µm CMOS (Vt:0.6 and -0.65V)
1V
1 mW
1 pF
Max. gain
Bandwidth
Input noise
Max. input current
Active area
210 kΩ
Ω
50 MHz
11pA/√
√Hz
40 µA
0.13 mm2
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Summary
! Low-voltage
TIA topology maximizes
PD bias voltage and output swing
! CMOS
TIA achieves 1V operation
without low-threshold devices
! Sub-1V
bias voltage doubler used for
the dynamic biasing of MOSFET
gates
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE