Download MEFT-SAD / 1º SEMESTER - 2016/2017 3rd Lab Guide

MEFT-SAD / 1º SEMESTER - 2016/2017 3rd Lab Guide
Lab Implementation and Test of ADC circuits. SAR ADC type and S&H
In the report present only the new subroutines that were NOT used in the previous
Labs. Show a phot os the circuits.
Grupo nº:
Alunos nº
Fig. 1. General Architecture of a type SAR ADC circuit
Objectives:
The goal with this activity is to implement in the lab a custom ADC cicuito of the SAR type
with a dedicated DAC SPI module and the necessary S&H circuit.
Equipment:
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Microcontroller board with microcontroller dsPIC30F4011 (version 3)
“MPLAB X” programming software and “C” compiler “XC16”
Electronic Test Bench with Signal generator / Digital Oscilloscope / Multimeter
Electronic “breadboard”
Electronic Switch TTL compatible 74HCT4066
Comparator swicth LM311
External SPI DAC chips MCP4921/MCP4821
Linux PC with a RS232 terminal app (e.g. Putty)
Procedures:
1rst Part: Assembling and testing a DC ADC:
1. Use a comparator chip in the breadboard powered by a +- 5V. Use a pull-up resistor
at the chip output tied to +V to assure it is logic TTL compatible. Test the circuit
with two analog voltages to check if it is working properly and to assure the output is
compatible with the dsPIC30F4011 Input PORT.
2. Connect this logic signal to a dsPIC30F4011 Input PORT and check the uProcessor
is reading the logic level. (Use a LED of a loopback output pin)
3. Assemble the circuit in the Figure 1 and write the SAR algorithm in code to generate
the bets and assemble the 12 bit converted value and transmit the raw values through
the RS232 interface. Don’t use number divisions on the code but instead bit shift
operations (e.g. 0x1<<i )
4. Characterize your converter using DC voltages in the following features:
a. Transfer function, INL, DNL
b. Resolution
c. Maximum sampling frequency
Procedimento:
1st Part: Assembling and testing an SAR ADC
5. Assemble the T&H circuit in the Figure 2 and include the voltage offset part to
assure the Vout voltage are in the same as the DAC output. Power the switch circuit
at 74HCT4066 at +5V/ GND
6. Test the circuit in the breadboard in terms of the settling time in the Hold -> Tracking
transition and the maximum voltage Droop slope in the Hold phase.
7. Implement a new output pin on the dsPIC30F4011 to control the S&H switch.
8. Modify your code to include correct timing for the switch and SAR algorithm,
periodic sampling and simple trigger function
9. Connect a sinus signal (~20 samples per signal period) and acquire 512 samples.
10. Annalise the signal and make and comprehensive comparison your ADC with the
one used in the Lab 1.
Fig. 2. Simple S&H (Track and Hold) circuit
Fig. 3. Simple Architecture of a Sigma Delta part of a type Sigma Delta ADC
Optional Part: Assembling and testing an ∑-∆ ADC
1. Design and implement a Sigma-Delta circuit capable of generating a binary bitstream
out of an analog signal (don’t use a S&H). Your 1-bit DAC shall be an output pin of
the dsPIC.
2. Acquire the X3 signal for some constant DC voltages Vin and comment them. Make
a code to count “1” bits on each group of 2N. Store the count and send them via
RS232. Draw the ADC Transfer function.
3. Use a slow variable input in the 0-5V range and store the maximum possible number
bits in the dsPIC RAM (pack 16 bits in each integer array element). Transfer all the
bits values to the PC.
4. Design a suitable Digital Low Pass (FIR or IIR) in MATLAB/Octave and obtain a
decimated multibit sample array. Plot it and analyse. Estimate the ∑-∆ ADC ENOB
figure.
See for example:
http://ww1.microchip.com/downloads/en/AppNotes/00700a.pdf
http://www.embeddedcodesource.com/codesnippet/ce005-using-fir-filters-from-dspicfilter-design-and-dsp-library