Download Integrated Circuits for Wireless Communiations

Illinois Center for
Wireless Systems
Integrated-Circuits Research for
Wireless Communications
Prof. Yun Chiu
Coordinated Science Laboratory
Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
Email: [email protected]
Executive Team
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Faculty: Deming Chen, Yun Chiu, Milton Feng, Ada
Poon, Elyse Rosenbaum, Naresh Shanbhag, Timothy
Trick, Martin Wong
30 graduate students
Analog/MMRF Integrated Circuits: (Chiu, Feng, Poon,
Rosenbaum, Trick)
VLSI for DSP and Communications: (Shanbhag)
Integrated Circuits Reliability: (Rosenbaum)
CAD for VLSI: (Chen, Wong, Trick)
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VLSI in Communications (Shanbhag)
Applied Communication &
Digital Signal Processing Theory
UIUC:LDPC
AT&T:LAN
VLSI Architectures
UIUC:MAP
AT&T:VDSL
Integrated Circuit Design
Intersymbol:EDC
Communication ICs
UIUC:ANT
Communicationsinspired SOC 3
VLSI in Communications (Shanbhag)
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Communication IC design
i FEC-based high-speed serial links (w/ Rosenbaum)
i Low-power turbo and LDPC decoders
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Communications-Inspired Design
i Stochastic sensor network-on-a-chip (w/ Doug Jones)
i System level power optimization of low-power links (w/ Andy
Singer)
i Error-resilient high-data rate 4G Viterbi decoders
i Robust SRAM design
i Joint equalization and coding for on-chip busses
i Low-power media kernels
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IC Reliability (Rosenbaum)
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Electrostatic discharge (ESD) events are unavoidable
during IC shipping, system assembly, and product
use
ESD causes catastrophic damage to CMOS ICs
On-chip ESD protection circuits are required
Protection circuits load high-frequency I/O pins,
degrading gain, impedance matching and noise
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i Develop protection circuits with minimal capacitance
i Co-design for performance and reliability
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Co-Design Example: UWB LNA (Rosenbaum)
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Transistor gm controls input
match
i gm selection depends on
CESD
Common-base topology has
power and area advantages
over the more typically used
common-emitter
A second LNA with no inductor
was also designed.
i Transistor size was halved
to maintain BW.
i Increased base resistance
increases NF.
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UWB LNA Measurement Results (Rosenbaum)
One-inductor CB
Zero-inductor CB
CE cascode*
[Ismail, ISSCC04]
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17.0 dB @ 2GHz
19.1 dB at 7GHz
16.1 dB
21 dB
-3dB BW
DC – 10 GHz
DC – 17 GHz
2 – 10 GHz
Noise Figure
4.7dB @ 10 GHz
5.65dB @ 10GHz
4.5dB @ 10GHz
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< -10dB
< -10dB
< -10dB
Linearity
-1dbCP = -17.1dBm
-1dBCP = -16.8dBm
IIP3 = 0dBm
VCC
2.7 V
2.7 V
2.7 V
Power dissipation
3.65 mW
3.65 mW
27 mW
ESD Protection
> 1.5 kV
> 1.5 kV
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Technology
0.18μm SiGe
BiCMOS
0.18μm SiGe
BiCMOS
0.18μm SiGe
BiCMOS
*3 inductors, largest area
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RF CMOS Research for Wireless Communication
Professor Milton FengFeng-HSIC Group at UIUC
HS
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CMOS Transceiver Design Research at HSIC
Circuit
Design
Device
Model
Noise Characterization and Model
for Submicron MOSFET
DSP
RF FRONT END
IQ Modulator
IQ Demodulator
DAC
DSP
ADC
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PA
900
LNA
DAC
ADC
VCO
PLL
Test Key Layout
Power Amplifier for Wimax
Characterization System
Low Noise Amplifier for UWB
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2
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4Gs/s Track & Hold Amplifier
Associated Gain Ga (dB)
NFmin (dB)
Model vs Data of a 130nm MOSFET
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Frequency (GHz)
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Analog/MMRF Integrated Circuits (Chiu)
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Adaptive Digital Calibration of Data Converters
i Low-power pipeline ADC (10-14 b, ≥100 MS/s) for WiMAX,
SDR
i Low-power interleaved ADC arrays (6 b, 1-10 GS/s) for
UWB, SONET
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Digitally Enhanced RF Circuits
i Digital adaptive equalization of WiMAX RF transmitter
i CMOS MIMO beamforming receiver for 802.11n (w/ Prof. A.
Poon)
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Comm. IC Building Blocks (Clock, P/DLL, CDR)
i Low-power dual-loop digital DLL for multi-phase clock
generation
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12b 400MS/s Pipeline ADC for SDR (Chiu)†
• Wiener filter-based adaptive digital background calibration
• Analog speed and accuracy decoupled into two separate paths
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In collaboration with UC Berkeley (P. Gray, R. Brodersen, and B. Nikolic)
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12b 400MS/s Pipeline ADC for SDR (Chiu)
Proposed solution
ADI 12401
ADC Architecture
Pipeline
Interleaving
Calibration method
LMS Dig. Bkgd.
Filter bank DSP
Resolution
12 bits
12 bits
SNR
65 dB
64 dB
Sample rate
400 MS/s
400 MS/s
Supply voltage
1.2 V
3.7/3.5/1.5 V
Reference voltage
1 V (diff. p-p)
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Power consumption
≤ 500 mW (analog)
6.8 W
Technology
0.13-μm CMOS
0.35-μm?
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Digitally Equalized WiMAX RF Transmitter (Chiu)
Prototype Design in 0.13-μm CMOS
Adaptive Digital Filter compensates PA nonlinearities (am-am, am-pm)
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Digitally Equalized WiMAX RF Transmitter (Chiu)
Ideal output spectrum
Distorted spectrum
Compensated spectrum
EVMRMS= 92%
EVMRMS= 4.2%
ACPR = 54 dB
ACPR = 67 dB
64QAM OFDM Modulation (WiMAX)
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m-1 MUX
1-m DEMUX
1GS/s 6b Low-Power ADC for UWB (Chiu)
Chip layout (2×2 mm2)
• Prototype implemented in 0.13-µm digital CMOS w/ 1.2-V supply
• Projected analog power consumption is 20 mW
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