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0.18μm CMOS 6GHz Pseudo Non-overlapping Clock Generator using High-speed Dividers MASAHIRO SASAKI†, SHIN YOKOYAMA‡, TAKASHI MATSUMOTO‡ † Advanced Research Institute for Science and Engineering, Waseda University ‡ Department of Electrical Engineering and Bioscience, Waseda University ‡ Graduate School of Science and Engineering, Waseda University 3-4-1 Ohkubo, Shinjuku-ku, Tokyo, 169-8555 JAPAN Abstract: - A parallel-serial converter must perform interleaving to achieve a 3Gbit/s (3Gbps) serial interface by using 0.18μm CMOS technology. In this paper, we propose three pseudo non-overlapping clock generators that use a high-speed 2:1 divider and operational frequencies of 1.89GHz to 3.23GHz, 2.27GHz to 4.76GHz, and 4.76GHz to 6.13GHz with a 1.8V power supply. Phase Noise calculated from the power spectrum was −147.0 dBc/Hz, −160.6 dBc/Hz, and −159.3dBc/Hz at 1MHz offset, and power consumption was 3.6mW, 3.2mW, and 5.0mW Key-Words: - Divider, Pseudo non-overlapping clock, Serial ATA, Ring Oscillator, Phase Noise 1 Introduction In recent years, ATA interfaces have been adopted for almost every internal hard disk excluding some servers and workstations. The rapid increase in recording density has been accompanied by the problem of speeding up the interface as hard disk capacity becomes larger. The Serial ATA standard was developed to guarantee speeding up the interface for ten years in the future, by replacing the conventional parallel interface with a high-speed single cable serial interface. Serial ATA defines a roadmap starting at 1.5Gbit/s (190MByte/s) in the first generation and migrating to 3Gbit/s (380MByte/s) in the second generation, then to 6Gbit/s (750MByte/s) in the third generation. Though it is easy to achieve when the latest process is used, this research seeks to realize a second-generation (3.0Gbit/s) circuit by using 0.18μm CMOS, which is near the speed limit of the device. It enables developing a transmitter and receiver circuit of Serial ATA. Figure 1 shows the block diagram of the Serial ATA transmitter. An internal parallel-serial converter should operate at the same frequency to obtain an output of 3Gbit/s, but it is difficult to achieve in this process. However, two interleaved parallel-serial converters have only to process data at a 1.5Gbit/s rate. To decrease glitch noise of the output signal, the two converters should not be turned on, simultaneously. However, it is difficult to control the timing of the clock by logic with a clock frequency near the operating limit of the process. This paper therefore utilizes an improved divider that exceeds 10GHz [1]-[5] to divide the output of a VCO operating at 6GHz (Fig. 1). It also proposes a circuit that generates a pseudo non-overlapping clock directly. Three high-speed dividers are proposed in section 2. Layouts of the proposed circuits are shown in section 3. Section 4 describes Phase Noise and shows simulation results of each divider. Section 5 concludes with a summary of the paper. 8 DATA Par/Ser DATA[i] , (i {2n | 0≤ n ≤7 | n Z}) AFE 8 DATA OUT OUT Par/Ser DATA[j] , (j {2n+1 | 0≤ n ≤7 | n Z}) CLK VCO VCLK Divider CLK Fig. 1 Serial ATA Block Diagram 2 High-speed Divider At a clock frequency near the operating limit of the process, it is difficult to control the timing of the clock by logic circuitry. In this chapter, we propose a circuit that divides oscillator’s output and generates a pseudo non-overlapping clock directly. Moreover, it was possible to suppress the influence of jitter by dividing the frequency. Though differential output oscillators are commonly available, it is difficult to construct a pseudo non-overlapping clock with them. edge of input clock. In addition, cross-coupled wiring at the output stage and adjusting the buffer produces a pseudo non-overlapping clock. e+ CLK+ TG1+ TG2+ OUT+ a+ 2.1 Conventional Divider CLK A conventional divider is achieved using a counter circuit as shown in Fig. 2. A D Flip-Flop must operate at high frequencies (GHz or more). Though designed to a minimum size with 0.18μm CMOS process by using TSPC ([6], [7]), a D flip-flop can operate at high speed, but it can only perform up to 3.2GHz for a single output or 2.8GHz for a complementary output. Three dividers utilizing a ring oscillator were therefore proposed and designed. d+ c+ b+ CLK- TG2- TG1- OUT- c- b- a- d- e- Fig. 3 Proposed five-stage differential Divider 1 T CLK+ CLK- D Q 1/2 CLK TG1+ ON OFF ON OFF ON OFF TG2+ OFF ON OFF ON OFF ON T1 CLK tinv a+ tinv ttg Fig. 2 Conventional Divider b+ c+ d+ 2.2 Proposed five-stage differential Divider 1 The circuit diagram of Divider 1 is shown in Fig. 3. This circuit consists of three CMOS inverters and two CMOS Transmission Gates (TGs). These are arranged in two parallel rings, so cross-coupling the output stages produces complementary outputs. Figure 4 shows Divider 1’s timing diagram. Operation on the +side is opposite to that on the –side, so only behavior on the +side is explained. The operation frequency of the three-stage ring oscillator in this divider is controlled by on-off switching of TG1+ and TG2+ with the input clock. This Divider doesn’t have theoretical minimum frequency because TG1 and TG2 alternately repeat turning ON and OFF. When CLK+ becomes LOW, TG1+ turns ON and the voltage level of node 'b+' changes to the same voltage level of node 'a+', with the propagation delay of TG. The transition in node 'b+' is propagated to node 'c+'. When CLK + becomes HIGH, TG1+ is turned OFF and TG2+ is turned ON, and it returns from 'c+' to 'a+' via 'd+' and 'e+'. When TG1 is turned ON again, the signal is propagated from node 'a+'. Consequently, the input clock is divided by two, triggered by the falling e+ ttg tinv tinv ttg ttg tinv tinv tinv tinv 2T Fig. 4 Timing diagram of Divider 1 2.3 Proposed four-stage differential Divider 2 Figure 5 shows the circuit diagram of Divider 2. Divider 2 has a circuit topology in which TG2 is removed from a single loop of Divider 1 [5] to enable operation at higher speed. This leads to improved speed in two ways. First, the delay of the critical path is reduced. The critical-path delay, which is from node 'a+' through nodes 'b+', 'c+', 'd+' and return back to node 'a+', is reduced by the delay of one TG. Second, the load the input clock must drive is reduced to half that in Divider 1. The input clock drives only TG. Thus the slope of the input waveform can be steep. This enables the clock to operate at higher frequencies and decreases the delay of TG because gate delay is eliminated due to the steep slope of the input waveform. Figure 6 shows the timing chart for Divider 2. The −side operation is just opposite that of the +side as in Divider 1. When TG is turned ON, the signal propagates from 'b+' to 'c+', then returns to 'b+' via 'c+', 'd'+, and 'a+'. After TG is turned ON again, the inverted signal propagates similarly. The input signal is thus divided by two. d+ CLK- TG OUT+ CLK c+ b+ a+ be decreased. Unlike in Divider 1 and Divider 2, a single loop of the four-stage ring oscillator doesn't oscillate by itself. However, it oscillates to make the signal of 'a+' and 'a−' complementary through the cross-coupling structure of the output stage. The operation frequency increased faster than that of Divider 2 because one inverter was removed and the propagation delay for one transition is less than in Divider 2. As illustrated in Fig. 8, when TG is turned ON, 'a+' and 'a−' are transmitted to 'c+' and 'c−' via 'b+' and 'b−'. It propagates from 'c+' to 'a−' as well as 'c−' to 'a+'. When TG+ is turned ON again, the signal propagates in the same manner. Therefore, the output is the input clock divided by two. CLK+ CLK- a+ TG OUT- a- c- b- b+ c+ out+ TG CLK CLK+ TG a- d- Fig. 5 Proposed four-stage differential divider 2 b- out- c- Fig. 7 Proposed three-stage differential Divider 3 T CLK+ CLK+ CLK- CLK- TG ON TG T2 tinv d+ a+ b+ c+ out+ ON OFF OFF ON OFF T3 tinv a+ ttg ttg ttg ttg tinv b+ tinv tinv tinv tinv tinv c+ tinv tinv a- tinv 2T b- tinv ttg ttg tinv tinv tinv Fig. 6 Timing diagram of divider 2 c- 2.4 Proposed three-stage differential Divider 3 The circuit diagram of Divider 3 is shown in Fig. 7. A pseudo non-overlapping clock was generated by changing the structure from a three-stage ring oscillator to a single loop of a four-stage ring oscillator (two stages for each side) and by intersecting wirings of the output taken from the second and fourth inverters. Thus, the propagation delay of Divider 3 can tinv 2T Fig. 8 Timing diagram of divider 3 2.5 Maximum and minimum frequencies Each divider has an upper and a lower operation frequency limit. Critical path delays T1, T2, and T3 of a divider yield the ranges. T1 ≤ T/2 T/2 ≤ T2,3 ≤ T (1) Here, the cycle of the input clock is T. The propagation delay of TG and the Inverter is assumed to be ttg and tinv. This yields the following. T1 = ttg+2tinv T2 = ttg+3tinv T3 = ttg+2tinv (2) The maximum and minimum input frequencies f1, f2 and f3 are obtained from f1 ≤ {2×(ttg+2tinv)}−1 {2×( ttg+3tinv)}−1 ≤ f2 ≤ { ttg+3tinv}−1 (3) {2×( ttg+2tinv)}−1 ≤ f3 ≤ { ttg+1tinv}−1 Fig. 9 Layout of Divider 1 3 Layout We have designed the proposed circuits with a 1Poly-5Metal-3Well 0.18μm Digital CMOS process. Figures 9 to 11 illustrate the layout of the high-speed dividers. As a result, the divider circuit areas are 25μm × 20μm = 500μm2 for Divider 1, 22μm × 21μm = 462μm2 for Divider 2, and 25μm × 21μm = 525μm2 for Divider 3. We performed the proposed circuit simulation including parasitic capacitance extracted from the layout using HSPICE. The simulation results show the tinv=34.9ps and ttg=48.9ps. The operation frequency ranges of proposed dividers are Fig. 10 Layout of Divider 2 f1 ≤ 4.21GHz for Divider 1, 3.26GHz ≤ f2 ≤ 6.52GHz for Divider 2, and 4.22GHz ≤ f3 ≤ 8.44GHz for Divider 3. However, since the output stages are utilizing the cross-coupling and the shifted timing of CLK+ and CLK− causes the difference of propagation delay, the simulation result became 1.00MHz ≤ f1 ≤ 3.23GHz for Divider 1, 2.27GHz ≤ f2 ≤ 4.76GHz for Divider 2, and 4.76GHz ≤ f3 ≤ 6.13GHz for Divider 3. Power consumption results are 3.6mW at 3GHz for Divider 1, 3.2mW at 4GHz for Divider 2, and 5.0mW at 6GHz for Divider 3. Figures 12 to 14 depict the simulation results when the input frequencies are assumed to be 3GHz, 4GHz, and 6GHz. Fig. 11 Layout of Divider 3 4 Phase Noise Fig. 12 Simulation result of Divider 1 at 3GHz input frequency 1.5 1 500m 0 1.5 1 500m 0 1n 2n 3n Time [s] Phase Noise is rapid, short-term, random fluctuations in the phase of a signal caused by time-domain instabilities. [8],[9] Because power-supply noise induces phase and frequency deviations in the output signal, the oscillator generates unnecessary energy spectra adjacent to the output frequency. Usually Phase Noise is expressed in decibels relative to carrier frequency power (dBc) at a constant offset frequency. Phase Noise was calculated from the power spectra using an ideal voltage source and noise voltage source added as shown in Fig. 15. Thirty sinusoidal signals with an amplitude of 5mV that depend on the harmonic components of the input frequency are added to the power supply voltage. The input is a pulse waveform of 3GHz for Divider 1, 4GHz for Divider 2, and 6GHz for Divider 3, and the rise/fall time is set to 50ps. Power spectra and Phase Noise results are shown in Figs. 16 to 21. Phase Noise that was calculated using a voltage source with noise added reached –147.0 dBc/Hz for Divider 1, –160.6 dBc/Hz for Divider 2 and –159.3dBc/Hz for Divider 3 at 1MHz offset. Figure 22 plots these Phase Noise as the input frequency to Dividers 1 to 3 is switched to each operable range and the offset frequency from carrier is switched from 100KHz to 10MHz. Though Phase Noise is increased to some extent by adding noise to the power supply, the noise of the three dividers is quite low. Therefore, the output frequency deviation will depend upon the VCO rather than the divider. 30 noise sources Fig. 13 Simulation result of Divider 2 at 4GHz input frequency 1.5 1.8V 1 Amplitude : 5mV Frequency : Harmonic component of input frequency Phase : Random Fig. 15 power supply with noise 500m 0 0 Power supply with noise Ideal power supply -20 -40 -60 VdB [dB] 1.5 1 500m -80 -100 -120 -140 -160 0 -180 1n 2n Time [s] 3n -200 1.4915 1.4965 1.5015 1.5065 Frequency [GHz] Fig. 14 Simulation result of Divider 3 at 6GHz input frequency Fig. 16 Power spectrum the Divider 1 1.5115 -100 Power supply with noise Ideal power supply -125 Phase Noise [dBc/Hz] Phase Noise [dBc/HZ] -100 -150 -175 -200 -225 -250 Power supply with noise Ideal power supply -125 -150 -175 -200 -225 -250 0.1 1 10 Offset Frequency [MHz] 0.1 1 10 Offset Frequency [MHz] Fig. 17 Phase Noise of Divider 1 Fig. 21 Phase Noise of Divider 3 0 Power supply with noise Ideal power supply -20 -100 -40 -80 -120 -100 -130 Phase Noise [dBc/Hz] VdB [dB] Divider1 Divider2 Divider3 -110 -60 -120 -140 -160 -180 -200 1.99 1.995 2 2.005 2.01 Frequency [GHz] -140 -150 -160 -170 -180 -190 -200 Fig. 18 Power spectrum the Divider 2 0.5 1 1.5 2 2.5 3 3.5 Output Frequency [GHz] Phase Noise [dBc/Hz] -100 Fig. 22 Phase Noise of various frequencies Power supply with noise Ideal power supply -125 -150 -175 5 Conclusions -200 -225 -250 0.1 1 10 Offset Frequency [MHz] Fig. 19 Phase Noise of Divider 2 0 Power supply with noise Ideal power supply -20 VdB [dB] -40 -60 -80 -100 -120 -140 -160 -180 2.991 2.996 3.001 3.006 Frequency [GHz] Fig. 20 Power spectrum the Divider 3 3.011 In this paper, we proposed three pseudo non-overlapping clock generators using high-speed 2:1 dividers. It was difficult to generate a pseudo non-overlapping clock with a clock frequency near the operating limit of the process. However, it can be achieved by placing two ring oscillators in parallel and utilizing cross-coupled wiring in the output stages. Divider 2 operated at higher speed and was designed by removing one TG from Divider 1. Divider 3 achieved additional speed with a single-loop ring oscillator of four stages. The operation frequency ranges of each divider are 1.89GHz ≤ f1 ≤ 3.23GHz for Divider 1, 2.27GHz ≤ f2 ≤ 4.76GHz for Divider 2, and 4.76GHz ≤ f3 ≤ 6.13GHz for Divider 3. The power consumption results are 3.6mW at 3GHz for Divider 1, 3.2mW at 4GHz for Divider 2, and 5.0mW at 6GHz for Divider 3. Phase Noise was calculated from the power spectra, and even with noise added to the power supply, the Phase Noise at 1MHz offset was –147.0 dBc/Hz for Divider 1, –160.6 dBc/Hz for Divider 2, and –159.3 dBc/Hz for Divider 3. The output phase noise is quite low, so the frequency deviation of the output will depend on the VCO, not the divider. This clock generator enables interleave operation for the parallel-serial converter. As a result, it is possible to realize a second-generation Serial ATA using a 0.18μm CMOS interface. Trial chip fabrication is now complete, and this circuit is being tested. We plan to report the results of circuit testing in the future. Then, 3.0Gbit/s transceiver and receiver circuits with this proposed divider are due to be designed. Acknowledgement This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc. The device was fabricated with the collaboration by Hitachi Ltd. and Dai Nippon Printing Corporation. References: [1] Tanabe, A. et al., “A 10 Gb/s demultiplexer IC in 0.18 μm CMOS using current mode logic with tolerance to the threshold voltage fluctuation,” IEEE ISSCC Dig. Tech. Papers, Feb. 2000, pp.62-63. [2] Razavi, B. et al., “A 13.4-GHz CMOS frequency divider,” IEEE ISSCC Dig. Tech. Papers, Feb. 1994, pp.176-177. [3] Kurisu, M. et al., “An 11.8-GHz 31-mW CMOS frequency divider,” Symp. VLSI Circuits Dig. Tech. Papers, June 1997, pp.73-74. [4] Wang, H., “A 1.8 V 3 mW 16.8 GHz frequency divider in 0.25 μm CMOS,” IEEE ISSCC Dig. Tech. Papers, Feb. 2000, pp.196-197. [5] Nogawa, M. et al., “A 16.3-GHz 64:1 CMOS FREQUENCY DIVIDER,” AP-ASIC 2000, 28-30 summary, AUG. 2000, pp.95-98. [6] Jiren Yuan, Christer Svensson, “High-Speed CMOS Circuit Technique,” IEEE J. Solid-State Cirsuits, VOL. 24, NO 1, FEB. 1989, pp.62-70. Jiren Yuan, Christer Svensson, “New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings,” IEEE J. Solid-State Cirsuits, VOL. 32, NO 1, JAN. 1997, pp.62-69. [8] Yalcin Alper Eken, John P.Uyemura, “A 5.9-GHz Voltage-Controlled Ring Oscillator in 0.18μm CMOS,” IEEE J. Solid-State Cirsuits, VOL,39 NO.1 JANUARY 2004 pp.230-233. [9] Weixin Kong, H. C. Lin, “A Low Phase Noise Fully Integrated 2-GHz CMOS LC VCO Design,” WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, Issue 1, VOL, 3 JAN. 2004 pp.54-58. [10] Kun-Nan Liao, Yo-Sheng Lin, “A Miniaturized Monolithic 2.4/5.7 GHz Concurrent Dual-Band Low Noise Amplifier Using InGaP/GaAs HBT Technology,” Proc. of 4th WSEAS Int.Conf. on SOLID STATE ELECTRONICS and PHYSICS, JAN. 2004 pp. 1651-1655 [7]