Download Arithmetic

Multiplication
Paper & Pencil
Computer
0110
x 0101
0110
x 0101
0110
00000
011000
0000000
0011110
0110
+ 00000
00110
+ 011000
011110
+ 0000000
0011110
Multiplicand
Multiplier
Product
Evolution of Multiplication Algorithm
1. First version of multiplication:
a. strategy;
It follows exactly the above method. The product of
multiplication of 32-bit register by 32-bit register is
 64 bits. Therefore the product register must be 64 bits.
Since, multiplicand shift left during each iteration during
the process, the multiplicand register must be 64 bits also.
From above:
$Mcand=64 bits
$Mplier=32 bits
$product=64 bits
1
b. Algorithm
START
C=1
No
Yes
$Mplier0=1
$Prod=$Prod+$Mcand
$Mplier, & $Mcand
C=C+1
Yes
C  32
No
Done
2
Example;
$Mcand=0110; $Mplier=0101; $Prod= 00011110
iteration
Step
$Mplier $Mcand
$Product
0
initial
0101 0000 0110 0000 0000
1
a. $Mplier0= 1;
0000 0110
$Prod=$Prod+$Mcand --------- ---- 0000 0110
2
3
4
END
b. $Mplier
0010
c. $Mcand
end of iteration 1
a.$Mplier0= 0;
no operation
------0010
-----
---- ----
---- ----
b. $Mplier
0001
---- ----
---- ----
c. $Mcand
end of iteration 2
a. $Mplier0= 1;
$Prod=$Prod+$Mcand
----0001
b. $Mplier
0000
c. $Mcand
End of iteration 3
a.$Mplier0= 0;
no operation
-----
0000
---- ----
---- ----
0000 1100 ----- ----0000 1100 0000 0110
0001 1000 ---- ---0001 1000 0000 0110
0001 1000
---- ---- 0001 1110
---- ----
---- ----
0011 0000 ---- ---0011 0000 0001 1110
-----
---- ----
---- ----
b. $Mplier
0000
---- ----
---- ----
c. $Mcand
End of iteration 4
----0000
0110 0000 ---- ---0110 0000 0001 1110
3
c. Hardware;
 ALU 64 bits.
 $Mcand 64 bits.
 $Mplier 32 bits.
 $Prod 64 bits.
Control decides when to
 Shift the $Mcand and $Mplier.
 When to write new values into the $Prod.
Note:
At each bit we need to have the following operations:
1. $Prod=$Prod+$Mcand.
2. Shift $Mcand left.
3. Shift $Mplier right.
If each of the above operation requires one clock cycle,
we need 96 cycles to multiply two 32-bit registers (3x32=96).
4
2. Second version of multiplication:
a. strategy;
Instead of shifting $Mcand left, shift $Prod right. The
digits of the two numbers will be the same. This will leads
to:
i. ALU=32 bits instead of 64 bits. This is huge
simplification in the hardware.
ii. $Mcand=32 bits instead of 64 bits.
iii. $Mplier=32 bits.
iv. $prod=64 bits.
b. Algorithm
START
C=1
No
$Mplier0=1
Yes
L.H. $Prod=L. H. $Prod+$Mcand
$Mplier, & $Prod
C=C+1
Yes
C  32
No
Done
5
Example;
iteration
0
1
2
3
$Mcand=0110; $Mplier=0101; $Prod= 00011110
Step
$Mplier $Mcand $Product
initial
0101
0110
0000 0000
a. $Mplier0= 1;
0110
L.H.$Prod=L.H.$Prod+$Mcand --------0110 0000
b. $Mplier
0010
----
---- ----
c. $Prod
end of iteration 1
a.$Mplier0= 0;
no operation
------0010
---0110
0011 0000
0011 0000
-----
----
---- ----
b. $Mplier
0001
----
---- ----
c. $Prod
end of iteration 2
a. $Mplier0= 1;
L.H.$Prod=L.H.$Prod+$Mcand
----0001
---0110
-----
----
0001 1000
0001 1000
0110
0111 1000
b. $Mplier
0000
----
---- ----
c. $Prod
4
END
----
0011 1100
End of iteration 3
a.$Mplier0= 0;
no operation
0000
0110
0011 1100
-----
----
---- ----
b. $Mplier
0000
----
---- ----
c. $Prod
-----
----
0001 1110
0000
0110
0001 1110
End of iteration 4
6
c.Hardware;
 ALU 32 bits.
 $Mcand 32 bits.
 $Mplier 32 bits.
 $Prod 64 bits.
3. Third version of multiplication:
a. strategy;
Since both $prod and $Mplier shift right, and the L.H.
$prod is 0’s at initial state, the $Mplier can be loaded in
the right half of the $prod. This eliminates the $Mplier
register, and therefore simplify the hardware.
7
b. Algorithm
START
C=1
No
$prod0=1
Yes
L.H. $Prod=L. H. $Prod+$Mcand
$Prod
C=C+1
Yes
C  32
No
Done
8
Example;
$Mcand=0110; $Mplier=0101; $Prod= 00011110
iteration
Step
$Mcand $Product
0
initial
0110
0000 0101
1
a. $Prod= 1;
0110
L.H.$Prod=L.H.$Prod+$Mcand
---0110 0101
b. $Prod
2
end of iteration 1
a.$Prod0= 0;
no operation
c. $Prod
3
end of iteration 2
c. $Prod0= 1;
L.H.$Prod=L.H.$Prod+$Mcand
----
0011 0101
0110
0011 0101
----
---- ----
----
0001 1010
0110
0001 1010
0110
0111 1010
----
c. $Prod
4
End of iteration 3
a.$Prod0= 0;
no operation
c. $Prod
END
End of iteration 4
0011 1101
0110
0011 1101
----
---- ----
----
0001 1110
0110
0001 1110
9
c.Hardware;
 ALU 32 bits.
 $Mcand 32 bits.
 $Prod 64 bits.
Signed Multiplication
Treat the multiplicand and multiplier as +ive numbers, then
the sign of the product will be +ive if both signs are similar and –
ive if they are different.
Hence, the shifting steps of the product would need to be
extend the sign of the product for signed numbers. This is called
Arithmetic Right Shift (ARS).
10
Booth Algorithm for Multiplication:
A more elegant approach to multiplying signed numbers.
START
C=1
$Prod0,-1
00
No operation
01
L.H. $Prod=L. H. $Prod + $Mcand
10
L.H. $Prod=L. H. $Prod - $Mcand
11
No operation
$Prod
C=C+1
Yes
C  32
No
Done
11
Example;
iteration
0
1
2
$Mcand=1011; $Mplier=0110; $Prod= 1110 0010
Step
$Mcand
$Product
initial
1011
0000 0110 0
a. $Prod0,-1=00;
No operation
------- ---- -
b. $Prod (ARS)
end of iteration 1
a.$Prod0,-1= 10;
L.H.$Prod=L.H.$Prod - $Mcand
---1011
----
0000 0011 0
0000 0011 0
1011 (sub)
0100 1’s
1
0101 2’s
0101 0011 0
3
b. $Prod (ARS)
end of iteration 2
a. $Prod0,-1= 11;
No operation
b. $Prod (ARS)
4
End of iteration 3
a.$Prod0,-1= 01;
L.H.$Prod=L.H.$Prod + $Mcand
b. $Prod (ARS)
END
End of iteration 4
---1011
0010 1001 1
0010 1001 1
----
---- ---- -
----
0001 0100 1
1011
----
0001 0100 1
1011
1100 0100 1
----
1110 0010 0
1011
1110 0010 0
12
Note: Switching the $Mcand and $Mplier does not alter the $prod.
$Mcand=0110; $Mplier=1011; $Prod= 1110 0010
iteration
Step
$Mcand
$Product
0
initial
0110
0000 1011 0
1
a. $Prod0,-1=10;
0110 (sub)
L.H.$Prod=L.H.$Prod - $Mcand
---1001 1’s
1
1010 2’s
1010 1011 0
b. $Prod (ARS)
2
3
----
1101 0101 1
end of iteration 1
a.$Prod0,-1= 11;
No operation
0110
1101 0101 1
----
---- ---- -
b. $Prod (ARS)
end of iteration 2
a. $Prod0,-1= 01;
L.H.$Prod=L.H.$Prod + $Mcand
---0110
----
1110 1010 1
1110 1010 1
0110
0100 1010 1
----
0010 0101 0
0110
0010 0101 0
0110 (sub)
1001 1’s
1
1010 2’s
b. $Prod (ARS)
4
End of iteration 3
a.$Prod0,-1= 10;
L.H.$Prod=L.H.$Prod - $Mcand
----
1100 0101 0
END
b. $Prod (ARS)
End of iteration 4
---0110
1110 0010 1
1110 0010 1
13
Note: Every compiler will substitute a “left shift” for a
multiply by a power of two.
Example:
1. 5x8=5x 2 3 =40.
5 = 0000 0101
Shift left 3 bits: 0010 1000 = 40.
2. -5x8 =-5x 2 3 =-40
5= 0000 0101
-5=1111 1010
1
1111 1011
Shift left 3 bits: 1101 1000=-40
Note:
MIPS has two instructions;
“mult”
for signed multiply.
“multu” for unsigned multiply.
mult $s0, $s1
multu $s0, $s1
Why not like this:?
mult $t0, $s0, $s1
multu $t0, $s0, $s1
Because the product
can not hold it.

64 bits. So, a 32-bit register like $to
When the product will be?
In two special registers $Hi: $Lo. $Hi holds the 32 MSB &
Lo holds the 32 LSB. That is why it is not necessary to
mention them in the “mlt” and “multu” instructions.
14
Division
Example:
5/3=1 with remainder 2
Divident=5
Divisor=3
Quotient=1
Remainder=2
Evolution of Division Algorithm
1. First version of division:
a. Strategy;
i.
Put divisor in L. H. of 64-bit $Div. Shift right to take
one bit at a time from dividend.
ii. Put Dividend in R. H. of 64-bit $Rem.
iii. Quotient will be in 32-bit $Qu. Initially set to 0.
b. Hardware: Divisor is 64-bit $Div, Dividend is 64-bit $Rem,
64-bit ALU, and 32-bit $Qu.
15
c. Algorithm;
START
C=0
C=C+1
$Div
$Rem = $Rem - $Div
No
$Rem < 0
Yes
$Rem = $Rem + $Div
$Quotient, 0
$Quotient, 1
Yes
C < 32
No
Done
16
Example;
$Rem=0000 0101; $Div=0000 0011; $Quotient= 0001, $Rem=0000 0010
itera
Step
$Div
$Qu
$Rem
2’comp.
tion
for $Div
0
initial
0011 0000 0000 0000 0101
1
$Div
0001 1000 ------- ---- 1110 1000
$Rem = $Rem - $Div
---- ------- 1110 1101
$Rem < 0
$Rem = $Rem + $Div
---- ----
----
0000 0101
$Qu, 0
---- ----
0000
---- ----
end of iteration 1
0001 1000 0000 0000 0101
2
$Div
$Rem = $Rem - $Div
0000 1100
---- ----
-------
---- ---- 1111 0100
1111 1001
$Rem < 0
$Rem = $Rem + $Div
---- ----
----
0000 0101
$Qu, 0
---- ----
0000
---- ----
end of iteration 2
0000 1100 0000 0000 0101
3
$Div
$Rem = $Rem - $Div
0000 0110
---- ----
-------
---- ---- 1111 1010
1111 1111
$Rem < 0
$Rem = $Rem + $Div
---- ----
----
0000 0101
$Qu, 0
---- ----
0000
---- ----
17
end of iteration 3
0000 0110 0000 0000 0101
4
$Div
$Rem = $Rem - $Div
0000 0011
---- ----
-------
---- ----
0001
---- ---- 1111 1101
0000 0010
$Rem > 0
$Qu, 1
END
end of iteration 4
---- ----
0000 0011 0001 0000 0010
At the end, the divisor is in the R. H. of $Div, the quotient is
in $Qu, the remainder is in $Rem.
2. Second version of division:
a. Strategy; Shift $Rem left instead of shifting putting the
divisor in the L. H. of 64-bit $div and shift right.
i.
Put divisor in 32-bit $Div.
ii.
Put Dividend in R. H. of 64-bit $Rem. Shift $Rem
left to take one bit at a time from dividend.
iii. Quotient will be in 32-bit $Qu. Initially set to 0.
b. Hardware: Divisor is 32-bit $div, Dividend is 64-bit
$Rem, 32-bit ALU, and 32-bit $Qu.
18
c. Algorithm;
START
C=0
C=C+1
$Rem
L. H. $Rem = L. H. $Rem - $Div
No
$Rem < 0
Yes
$L. H. Rem = L. H. $Rem + $Div
$Quotient, 0
$Quotient, 1
Yes
C < 32
No
Done
19
Example; Div=0011 2’s comp=1101
$Rem=0000 0101; $Div=0011;
$Quotient= 0001, $Rem=0010 0000
itera
Step
$Div $Qu
$Rem
tion
0
initial
0011 0000
0000 0101
1
$Rem
---0000 1010
L. H. $Rem = L. H. $Rem - $Div
---1101 1010
$Rem < 0
$L. H.Rem = L. H. $Rem + $Div
----
0000 1010
0000
---- ----
end of iteration 1
0000
0000 1010
$Rem
L. H. $Rem = L. H. $Rem - $Div
-------
0001 0100
1110 0100
$Rem < 0
L. H. $Rem = L. H. $Rem + $Div
----
0001 0100
end of iteration 2
0000
0000
---- ---0001 0100
$Rem
L. H. $Rem = L. H. $Rem - $Div
-------
0010 1000
1111 1000
$Rem < 0
L. H. $Rem = L. H. $Rem + $Div
----
0010 1000
0000
---- ----
0000
0010 1000
$Qu, 0
2
$Qu, 0
3
$Qu, 0
end of iteration 3
20
4
$Rem
L. H. $Rem = L. H. $Rem - $Div
-------
0101 0000
0010 0000
$Rem > 0
$Qu, 1
END
0001
end of iteration 4
0001
0010 0000
At the end, the quotient is in $Qu, the remainder is in L. H. of
$Rem.
3. Third version of division:
i. a. Strategy: let the L. H. $Rem to represent the
Quotient. This will eliminate the $Qu.
c. Hardware: Divisor is 32-bit $div, Dividend is 64-bit
$Rem, and 32-bit ALU.
21
c. Algorithm;
START
C=0
C=C+1
$Rem
L. H. $Rem = L. H. $Rem - $Div
No
Yes
$Rem < 0
$L. H. Rem = L. H. $Rem + $Div
$Rem, 0
$Rem, 1
Yes
C < 32
No
Done
22
Example; Div=0011 2’s comp=1101
$Rem=0000 0101; $Div=0011; , $Rem=0010 0001
itera
Step
$Div
$Rem
tion
0
initial
0011 0000 0101
1
$Rem, 0
0000 1010
L. H. $Rem = L. H. $Rem - $Div
1101 1010
$Rem < 0
$L. H.Rem = L. H. $Rem + $Div
0000 1010
end of iteration 1
0000 1010
$Rem, 0
L. H. $Rem = L. H. $Rem - $Div
0001 0100
1110 0100
$Rem < 0
L. H. $Rem = L. H. $Rem + $Div
0001 0100
end of iteration 2
0001 0100
$Rem, 0
L. H. $Rem = L. H. $Rem - $Div
0010 1000
1111 1000
$Rem < 0
L. H. $Rem = L. H. $Rem + $Div
0010 1000
end of iteration 3
0010 1000
$Rem,0
L. H. $Rem = L. H. $Rem - $Div
0101 0000
0010 0000
2
3
4
23
END
$Rem > 0
Set the LSB of $Rem to 1.
0010 0001
end of iteration 4
0010 0001
At the end, the quotient is in R. H., and the remainder is in L.
H. of $Rem.
Signed Division
1- Negate the quotient if signs of dividend and divisor are
different.
2- The remainder has the same sign of dividend.
Divide in MIPS
The same hardware can be used for both multiply and divide;
Hardware
32 bits register
32 bit ALU
64 bit register
Multiply
Mcand
+
Product
Divide
Divisor
+, Remainder + Quotient
Note:
MIPS has two instructions;
“div” for signed division. [div $s0, $s1]
“divu” for unsigned division. [divu $s0, $s1]
$Hi holds the 32 MSB (remainder) & Lo holds the 32
LSB (quotient).
To have the remainder and the quotient from Hi and Lo;
Mfhi $s1
$s1=Hi {move from Hi}
Mflo $s1
$s1=Lo {move from Lo}
24
Floating Point
Decimal
 =3.14159
nano second=1.0x 10 9 second
Century=100(year) x 365(day) x 24(hour) x 60(min) x 60(sec)
=3153600000 sec
=3.1536x 109 sec. This number can be hold in a 32-bit
register.
What to do?
Store it as floating point.
Binary
0.000101
=1.01x 10 3
=10.1x 10 5
=101.0x 10 6
normalized scientific notation.
not normalized
not normalized
Floating point representation
The float point representation in a 32-bit register can be:
8 bits Exp
23 bits (significant)
1 bit
sign
Floating number  (1)s x Significand x 2exp
The trade-off is between accuracy (the size of significant)
and range (the size of exponent).
25
Overflow: Exponent is too large to fit in the exponent field.
Underflow: Negative exponent is too large to fit in the
exponent field.
IEEE 754 floating point
Double precision: To avoid overflow, underflow, and to
increase accuracy.
11 bits Exp.
52 bits (significant)
1 bit
sign
Each floating point binary numbers that normalized to
computer notation has a digit “1” in the MSB for significant. In
IEEE 754 the leading 1 bit of normalized binary numbers implicit.
So, there are 24 bits and 53 bits for significant in single and double
precision, respectively.
Floating number  (1)s x (1  Significand ) x 2exp
where
0  significan t  1
Note:
The signed floating number is represented in sign and
magnitude form here.
What about the sign of the exponent?
1- Sign and magnitude. This is what it was. It is not good for doing
sorting for example.
26
2- Bias notation (IEEE 754): All exponent values will be +ive.
This is done by adding the largest possible –ive value in its sign
and magnitude approach (bias). This makes sorting easer.
In single precision the largest –ive number is -127 (1000
0000) and the largest +ive number is 127 (0111 1111). In order to
convert all exponent values to +ive, we have to add the bias (127)
to the original value of the exponent. So, the exponent will range
from 0 to 254.
In double precision the largest –ive number is -1023
(10000000000) and the largest +ive number is 1023 (011 1111
1111). In order to convert all exponent values to +ive, we have to
add the bias (1023) to the original value of the exponent. So, the
exponent will range from 0 to 1023.
The real value of a number is;
Floating number  (1)s x (1  Significand ) x 2exp bias
Example:
Show the representation of 0.8 in single and double precision
form.
(0.8)10  (0.1101 1101 1101 ....)2  1.101 1101 1101 * 21
in bias representation the exponent is -1+bias=-1+127=126
(126)10  (01111110) 2
0
01111110
101 1101 1101 1101 1101 1101
1 bit
sign
Exponent in double precision -1+bias=-1+1023=1022
(1022)10  (01111111110) 2
0
01111111110
101 1101 1101 …. 1101 1101 11
1 bit
sign
27
Floating point addition
START
Equal the exponents of the two floating
point numbers by shifting the significant
of the smaller number to the right.
Add the significant
Normalize the sum shifting right (left),
and increment (decrement) the exponent
Overflow or
underflow
No
Yes
Exception
Round the significant of the sum
No
Normalized
Yes
Done
28
5
6
Example: 0.110011* 2 +0.11101* 2 .
1. The exponents of the two number must be 6;
6
0.0110011* 2 +0.11101* 2
6
2. Add the significant;
0.0110011* 2
6
+ 0.1110100* 2
6
Sum= 1.0100111* 2
6
3. Normalize the sum shifting left one bit;
Sum= 0.10100111* 2
7
4. in single precision;
Sum=0.101001110000000000000000* 2
0000 0111
5. The layout is:
0
0000 0111
0100 1110 0000 0000 0000 000
1 bit
sign
Note:
 The exponent 0000 0000 is reserved for 0 in floating
point. It does not represent the exp(-127) as we
mentioned before.
 The exponent 1111 1111 is reserved for indicating
values and situation outside the scope of normal
floating point number.
 126  exp onent  126
So, in single precision
In double precision  1022  exp onent  1022 .
29
Floating point multiplication
START
Add the biased exponent of the two numbers,
then subtracting the bias from the sum to get
the new biased exponent
Multiply the significant
Normalize the product
Overflow(exp>254)
or underflow( exp<1)
No
Yes
Exception
Rounding
No
Normalized
Yes
Set the sign of the product
Done
30
Example:
(0.6)x(-0.45)=?
1
0
0
1
60
20
40
80
60
(0.6)10  (1001...) 2  (1.0011...) 2 * 2 1
0
1
1
1
0
0
45
90
80
60
20
40
80
(0.45)10  (1.1110 ...) 2 * 22
1
1.0011 * 2
2
1.1110 * 2
00000
100110
1001100
10011000
100110000
3
1.00111010 * 2
 126  exp onent  3  126 , no underflow & no overflow.
The result is normalized. So, round the number (assume the
significant is four digits: 1.00111010=1.0100.
3
Sign of the product is -. So, the product is: -1.0100* 2
31
MIPS Instructions
add.s $f2, $f4, $f6
sub.s $f2, $f4, $f6
add.d $f2, $f4, $f6
sub.d $f2, $f4, $f6
R-type
R-type
mul.s $f2, $f4, $f6
div.s $f2, $f4, $f6
mul.d $f2, $f4, $f6
div.d $f2, $f4, $f6
R-type
R-type
lwcl $f1, 100($s2)
swcl $f1, 100($s2)
I-type
I-type
bclt 25 if condition is true go to address PC+4+100. I-type
bclf 25 if condition is false go to address PC+4+100.I-type
c.lt.s $f1, $f2 if $f1<$f2 condition 1, else condition 0.I-type
c.lt.d $f1, $f2 if $f1<$f2 condition 1, else condition 0.I-type
Accurate Arithmetic
No more than 24 bits can be represented in single precision.
No more than 53 bits can be represented in double precision.
Rounding
Since limited number of digits can be represented in the
register, rounding must be done.
Rounding in MIPS
There are two extra bits on the right of the register (guard-bit
& round-bit) evolved during intermediate calculations.
32
33