Download Homework Assignment #2

ECE 5040
25 September, 2012
Fall 2012
Howard Luong
Advanced Analog Integrated-Circuit Design
HW 2 – Noise Analysis
(Due at 6PM on October 24th)
1.
1. 1. Razavi, Problem 7.3
Using the distributed model of Fig.1 and ignoring the channel thermal noise, prove that for
gate noise calculations, a distributed gate resistance of RG can be replaced by a lumped
resistance equal to RG/3. (Hint: Model the noise of RG by a series voltage source and
calculate the total drain noise current.)
n
Hint:
2
i 
i 1
n(n  1)(2n  1)
6
Fig. 1
2. Estimate and compare the total equivalent input and output noise voltages for the following
CMOS amplifiers in Fig. 2 using the 0.18-m CMOS process parameters obtained from HW
#1. Assume that RL = 1 K, RS = 0.1 K, and that all transistors (except M3D) are biased at 1
mA each with gm = 10mA/V. Ignore the flicker noise. Include the SPICE simulation.
Fig. 2
3.
Razavi, Problem 7.12
Assume λ=γ=0, calculate the input-referred thermal noise voltage of each circuit in Fig.
3. For Circuit (a), assume gm3,4 = 0.5gm5,6.
Fig. 3
4.
Gray, et al, Problem 11.9
A BiCMOS Darlington is shown in Fig. 4. Neglecting frequency effects, calculate the
equivalent input noise voltage and current generators for this circuit, assuming that the
dc value of Vi is adjusted for IC1 = 1mA. Device data is μnCox = 60μA/V2, Vt = 0.7V, λ
= 0, γ = 0, W = 100μ, L = 1μ for the MOSFET and IS = 10-16A, VA = ∞, β = 100, rb =
100Ω for the bipolar transistor.
Fig. 4
5.
Razavi, Problem 7.21
Design the circuit of Fig. 5 for an input-referred thermal noise voltage of 3nV/Hz1/2
and maximum output swing. Assume ID1 = ID2 = 0.5mA, VDD = 1.8V. Use the 0.18-m
CMOS process parameters obtained from HW#1 and verify with SPICE simulation.
Fig. 5