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4. Logic Gates
4. LOGIC GATES
The gates, the logic or digital gates, are electronic devices, which realize elementary logic
functions. The same functions can be realized by different circuits. The different circuits' gates
are with different ratings for speed, power consumption, temperature range, voltage levels,
current levels, and resistance to disturbing signals. Basically, there are three commonly used
families of integrated-circuit logic gates: TTL (transistor-transistor logic), CMOS (complementary metal oxide semiconductor), and ECL (emitter-coupled logic). Within each family,
several subfamilies or series of logic gates are available.
4.1. Bipolar Transistors Logic Gates
In this chapter the bipolar transistor switch and various logic gates of bipolar transistors are
investigated.
4.1.1. BJT Switch
Switch is one of the main components of any logic circuit. Electronic switches of integrated
technology are reliable and high-speed; they ensure small power consumption and low price.
We will formulate the main requirements to switches for logic gates:
1. Small resistance of closed switch and large resistance of open switch.
2. High speed of operation.
3. Uncoupling of control circuit and switching circuit.
4. Interference immunity.
BJT switches have high-speed operation, small resistance of closed switch. Control
circuit of BJT switches (base-emitter) is not separated from
+ EC
switching circuit (collector-emitter).
BJT switch is a simple common-emitter DC-coupled
RC
U C = U OUT amplifier stage. It is made up from two main components: BJT
(active device of amplifier stage) and resistor in collector circuit
VT
Rc – a load of amplifier stage.
U IN
Operating point of BJT in switch circuit moves between an
off state and a saturated state. When the BJT is in saturation,
output voltage (voltage on a saturated Si transistor) is about 0.2 V
– it is a low level UL, or U0, or logic 0. When the BJT is off,
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4. Logic Gates
output voltage equals to power supply voltage
IC
Ec (Ic  0, and IcRc  0) – it is a high level
EC
I B = I BS
UH, or U1, or logic 1.
RC
AS
High level of input voltage biases the
transistor into saturation and makes a low level
at output. Low level of input voltage biases the
transistor into off state and makes a high level
at output. It means that BJT switch operates as
inverter.
I B = 0 I B = –I C0
AOFF
Now we will perform more detailed
0
UC
U CS = U 0
U COFF = U 1 E C
analysis of BJT switch according BJT common-emitter output characteristics.
According the switch circuit
UC = EC – IC  RC .
In the system of axes IC, UC it is an equation of a straight line. We will find two points of
this line.
If UC = 0, IC = EC / RC . If IC = 0, UC = EC .
The line across these two points is a load line of BJT switch. The intersection of this line and
output characteristic of BJT defines an operating point of switch transistor.
If UIN = U0 = (0.1 – 0.2) V, both junctions of the transistor are reverse-biased and
IB0 = – (IC 0 + IE 0)  – IC0 , because IC0  IE0.
The operating point of the transistor in off state AOFF is an intersection of the load line and the
output characteristic IB = – IC 0 . It means that output voltage in off state
UOUT = UCAOFF = U1  EC .
The resistance of open switch rAOFF = U1/ IC0  EC / IC0 – it is tens and hundreds of
Megaohms. When the base circuit is open, IB = 0, and the value of corresponding collector
current is greater, and the value of resistance of open switch is less.
If UIN = U1  EC, both junctions of the transistor are
n
forward-biased. The BE junction is saturated, and BC junction is
– +
only forward-biased.
0.5 V
ICS = (EC – UCS)/RC = (EC – U0)/RC  EC / RC ,
+
p
0.2 V
the corresponding base saturation current IBS = ICS /. If base
+
current increases above IBS, saturation current of collector ICS does
0.7 V
not increase, because operating point As is defined by load line,
– –
that is, by RC and EC. Operating with IB  IBS is unwelcome,
n
because in this case more majority carriers are accumulated near
collector junction. It means long extraction time of charge carriers when the junction is reverse
biased, or long switch closing time.
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4. Logic Gates
There are two reasons of long switch closing time. One is just
mentioned internal reason: extraction time of the charge carriers
when the forward-biased junction becomes reverse biased. The
RC
UC = UOUT
second reason – external: long time of charge of capacitor Cload
with time constant RC  Cload .
VT
There are no internal processes that prolong switch opening
Rload
Cload time. Reverse-biased junction opens after forward-biasing without
delay. External process – discharging of capacitor Cload through a
small resistance of saturated transistor – is short. All stated above
explains the shape of a pulse at the BJT switch output.
The main characteristic of the switch is its complete
UOUT
transfer characteristic: dependence of output voltage from
U1
input voltage.
There are three regions of the characteristic.
01
1 0
When input voltage is less than 0.5 V (forwardbiasing voltage of Si junction), the transistor is in cutoff
state. The output voltage UOUT = U1  EC.
U 00
t
When input voltage is more than 0.7 V, transistor is
in saturation state. The output voltage UOUT = U0  0.2 V.
UOUT
Between these two regions of saturation state and
1
cutoff
state
U  EC
cutoff state there is a region in which transistor operates in
amplifying state
amplifying state – it is a short time interval when switch
saturation state
opens or closes.
01
Uinterference immunity
Interfering signal of positive voltage that is greater
10
10
than Uinterfer.immun. opens the closed switch changing its
Uinterference immunity
output level from U1 to U0. Interfering signal of negative
01
UIN voltage that is greater than Uinterf.immun. closes the opened
U0
0 U0 0.7 V
switch changing its output level from U0 to U1. It is
U1 EC
0.5 V
obvious, that interference immunities from 0 to 1 and from
0 to 1 of BJT switch are unequal.
+ EC
4.1.2. From DCTL to TTL
In Direct-Coupled Transistor Logic (DCTL) all transistors operate with a common load RC in
collectors' circuit. Such circuits of logic gates are named as a collector-coupled circuits.
Operating of unloaded gate
Let us assume that loading gates with transistors VT4 and VT5 are not connected to the output
of our gate. Then and only then when low levels are in all inputs A, B, and C, all transistors
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4. Logic Gates
VT1, VT2, and VT3 are closed, there is
no current through resistor RC and there
is no voltage drop on this resistor. It
means that
VT1
UOUT = U1 = EC.
UIN1
If there is a high level in one
input at least, the current flows through A
RC and the transistor, opened by high
level in input. An output voltage is the
voltage on the saturated transistor:
+ EC
VT4
F= A+ B+ C
RC
VT3
VT2
UIN2
B
UIN3
C
UOUT
VT5
UOUT = U0 = EC – IC opened trans.  RC = UCS  0.2 V.
Exceptional combination of all 0s in inputs indicates the logic operation OR; because all 0s in
inputs create not 0 but 1 in output, it is the logic operation NOR. The gate is 3NOR gate, 3
indicates the quantity of logic inputs.
Unloaded DCTL gate ensures great logic swing – the difference of high and low levels:
UL = U1 – U0 = EC – 0.2 V  EC .
Operating of loaded gate
Let us assume that loading gates with transistors VT4 and VT5 are connected to the output of
the gate. Logic networks are made from one type of gates, therefore loading gates are the same
as the loaded gate. High level at the gate output, created by 0s in all inputs, opens transistors of
loading gates VT4 and VT5. The BE junctions of these transistors are saturated. It means that
high level in the output of the loaded gate now is quite different:
UOUT = U1 = EC – (IINVT4 + IINVT5 + ...) RC = Us  0,7 V.
When the level in the gate output is low, the loading transistors are in off state. The reversebiased BE junctions of loading gates VT4 and VT5 do not change the voltage of low level, it
remains 0.2 V.
Logic swing in the output of the loaded DCTL gate is quite small:
UL = U1 – U0 = US – 0.2 V = 0.7 V – 0.2 V = 0.5 V.
Small logic swing means small interference immunity.
Low high level and small logic swing are the faults of principle. They are the reason,
why DCTL gates are not used today.
In Resistor Coupled Transistor Logic (RCTL) these two disadvantages are nearly
eliminated. In the base circuit of every RCTL transistor are series connected resistors RB with
resistance RB  rINBE of the saturated transistor. It means that a voltage drop on this resistor
URB  UrINBE and U1RCTL  U1DCTL . But RCTL has another fault of principle: resistors
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4. Logic Gates
+ EC
with large resistance occupy a lot of space on the chip of
integrated circuit, and that is why the RCTL is not used
R5
today. We will look into one version of RCTL gate only
F= A+ B+ C
R1
therefore, that it is a transitional version to DTL.
A
VT
It is always possible to choose such ratio of
R2
resistances R1 and R4 and such – E, that only 0s in all
B
inputs set the transistor in a cutoff state. If there is a high
R3
R4
C
level in one input at least, the transistor is saturated. It is
obvious, that the gate performs logic operation 3NOR.
–E
When resistors are exchanged for diodes, the main
disadvantage of RCTL – large area of resistors on
integrated circuit chip – disappears, and we
+ EC
have a DTL. Diode-Transistor Logic is a
transitional version to TTL.
R3
R1
F=
A
B
C


Then and only then when high levels are
VD1
A
in all inputs A, B, and C, all diodes VD1, VD2,
VT
VD4
VD5
VD2
and VD3 are in cutoff state. Current through
B
R1 is small, high voltage of point D saturates
D
VD3
the transistor. There is a low level in the output
R2
C
– the voltage on the saturated transistor.
If there is a low level in one input at
–E
least, the corresponding diode is saturated. The
current through R1 and saturated diode creates
a low voltage in point D. The transistor is in
+ EC
cutoff state, and that means a high level at
output.
R1
The gate realizes a logic function
V D5
V D4
V D1
3NAND. Another conclusion from description
– 0.7 V + + 0.7 V – + 0.7 V –
of operation is such: R2  R1. The large reB
A
sistance of R2 ensures small current through
D
–
+
+ F
+
R1 (+ EC - R1- VD4 -VD5 - R2 - –E) when all
R2
0.5 V
0.2 V
0.2 V
0.9 V
diodes are cutoff. The small resistance of R1
–
ensures great current in the circuit + EC - R1–E
+
–
–
saturated diode with low level in input saturated transistor of the loaded gate with low
level at output - ground.
It is necessary to discuss the destination of diodes VD4 and VD5. Let low level 0.2 V
acts in input A. The voltage on the saturated diode VD1 is 0.7 V. It means that voltage of point
D is 0.7 + 0.2  0.9 V and it is not low level for transistor. The current in the circuit + EC - R1 R1 = R2 = R3
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4. Logic Gates
VD4 - VD5 - R2 - –E makes voltages of 0.7 V on the saturated diodes VD4 and VD5. The
voltage on the diode VD4 decreases voltage of point D from 0.9 till 0.2 V – restores a low level
in the point F. The voltage on the diode VD5 decreases a base voltage of the transistor (point B)
till – 0.5 V, so increasing the interference immunity of the gate.
Now we can formulate the conclusion: diode VD4 is indispensable for proper operation
of gate; diode VD5 is not indispensable, it only makes better properties of the gate. VD4 is the
low level restoring diode, VD5 is the low level decreasing diode.
DTL gates have one exceptional merit: high logic level at output makes a cutoff state of
input diodes of the loading gates. It means, that a high level in the output of DTL gate remains
high independently of loading the gate.
Example 4.1
How many isolated areas are necessary for components of DTL gate in integrated circuit produced by standard
BJT technology? Which junction of transistor – BE or BC – is proper for input diodes of DTL gate?
The conclusion from example 4.1 is such: all input diodes and the low level restoring
diode can be made up as one input transistor. Then we have TTL.
4.1.3. TTL Gates
In the TTL (Transistor-Transistor Logic) family, logic elements are made from NPN BJTs,
diodes, and resistors. TTL was one of the first digital technologies to be developed and has
been a traditional choice in systems where high computational speed is required but power
consumption is not a concern. Most TTL logic gates are available as of-the-shelf components
packaged as multipin LSI level integrated circuits. Compared with MOSFET-based logic
families, TTL components are far less susceptible to physical damage from the electrostatic
discharge that occurs during manual handling of components. For these reasons, the TTL logic
family is ideal for laboratory 'breadboarding" of digital systems designs.
Simple TTL gate
BE junctions of the multiemitter transistor VT1 replace
input diodes VD1, VD2, VD3 of DTL gate; BC junction
of VT1 replaces the low level restoring diode VD4.
Interference immunity of this simple TTL gate is less
than interference immunity of the basic DTL gate,
because there is no low level decreasing diode VD5. The A
topology (view downstairs) and cross-section of a TTL B
multiemitter transistor show that all input diodes and C
low level restoring diode are located in only one isolated
area; all components of this simple TTL gate can be
located in three isolated areas only.
+ EC
R1
V T1
R3
F= A B C
V T2
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4. Logic Gates
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