Download Process Size Optimal Input Mean Leakage Reduction

Ashley Brinker
Karen Joseph
Mehdi Kabir
ECE 6332 – VLSI
Fall 2010
Outline
• Motivation & Approach
•Input Vector Control
• MTCMOS
• 16-bit Adder
• Results
• Conclusion
Idle Leakage Current
Subthreshold Leakage
• MOSFET gate cannot completely turn off
the drain-source current in transistor.
• Due to various factors such as weak
inversion, carrier concentration gradients,
and thermal effects.
Gate Leakage
• Current through the transistor caused by
band-to-band tunneling of carriers through
the gate.
• Occurs when there is a large VGS or VDG
bias.
1
0
0
0
0
1
1
0
1
0
1
0
Motivation
• As transistors are scaled down,
gate leakage becomes a larger
proportion of the total leakage.
40
• Using
subthreshold
reduction
techniques can sometimes lead to
an increase in gate leakage or vice
versa.
• In many cases, better leakage
reductions can be achieved by
optimizing gate leakage current first.
Gate Leakage (%)
35
30
25
20
15
130
90
65
Process Size (nm)
45
32
Methodology
• First tried to optimize circuit using input vector control.
• Heurisitic for determining an optimal input vector for
arbitrary circuit.
• Looked at MTCMOS as a method of reducing
subthreshold leakage and gate leakage.
• Analyzed tradeoffs between leakage reduction and
delay.
• Applied it to a complex circuit: 16-bit ripple carry adder.
Leakage Minimization: Input Vector Control
• Leakage current is data dependent. Input
vector control chooses the best input that
minimizes the total leakage.
• As process size is decreased, gate leakage
becomes a more significant portion of the
total leakage.
1.6
-8
8
Subthreshold
Gate
1.2
6
1
5
0.8
0.6
3
2
0.2
1
000
001
-8
4
0.4
0
x 10
7
Current (A)
Current (A)
1.4
x 10
010
011
100
Input Vector
101
130nm NAND3 gate
110
111
0
000
001
010
011
100
Input Vector
101
32nm NAND3 gate
110
111
Optimum Input Vector
• Finding
the optimum input vector for an arbitrary circuit is a NPcomplete problem.
• Possible Solution: Use exhaustive search to find best vector. Not
useful for circuits with large number of inputs.
• Near-optimal Solution: For large circuits using a Monte Carlo
search or genetic algorithms can yield input vectors which are
better than average.
• Near-optimal Solution: Use a type of greedy search heuristic to
find the input vector which minimizes a cost function.
Optimum Input Vector
Heuristic Outline
2
3
4
5
Generate a node controllability list for
each node in circuit.
Find the best case input for each gate in
circuit based on total leakage and node
controllability.
Determine conflicting and dominating
cells.
Use a cost function which penalizes
gates not in best case input or ones
which force conflicts and rewards gates
which dominate the most of the other
cells.
3.5
x 10
-8
Subthreshold
Gate
3
Leakage Current (A)
1
2.5
2
1.5
Choose gate with the minimum cost
1
function and satisfy its best case input.
Repeat process until all input vectors are 0.5
set to a value.
0
00
01
Input Vector
10
2-input XOR gate
11
Optimum Input Vector: Example
Optimum Input Vector: Full Adder
1
x 10
-6
Process Size
Optimal Input
Mean Leakage
Reduction
130 nm
A=0000 0000 0000 0000
B=0000 0000 0000 0000
Cin=0
17.6%
32 nm
A=0000 0000 0000 0000
B=1010 1010 1010 1010
Cin=1
28.3%
Subthrehold
Gate
0.9
Leakage Current (A)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Input Vectors
MTCMOS
SLP
•Input Vector = 111
•SLP = 1
•VDD = 1.0 V
•High VT - from .4 to .95 (in .5
intervals)
____
SLP
•Low VT - default (0.4)
Subthreshold Current using MTCMOS
1.00E-06
0.4
0.6
0.8
1
1.00E-07
32nm Subthreshold Current
45nm Subthreshold Current
Axis Title
1.00E-08
65nm Subthreshold Current
1.00E-09
90nm Subthreshold Current
130nm Subthreshold
Current
1.00E-10
1.00E-11
Axis Title
Gate Leakage Current using MTCMOS
0.4
0.5
0.6
0.7
0.8
0.9
1
1.00E-10
32nm Gate Leakage Current
1.00E-11
45nm Gate Leakage Current
65nm Gate Leakage Current
1.00E-12
1.00E-13
Total Leakage Current using MTCMOS
1.00E-07 0.4
1.00E-08
0.5
0.6
0.7
0.8
0.9
1
32nm Total Leakage Current
45nm Total Leakage Current
65nm Total Leakage Current
1.00E-09
90nm Total Leakage Current
1.00E-10
1.00E-11
130nm Total Leakage
Current
Subthreshold Leakage Reduction using MTCMOS
5.00E+03
4.50E+03
4.00E+03
3.50E+03
3.00E+03
32nm
45nm
2.50E+03
65nm
90nm
2.00E+03
130nm
1.50E+03
1.00E+03
5.00E+02
0.00E+00
0.4
0.5
0.6
0.7
0.8
0.9
1
0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
1.00E-28
Current x (Delay)2
1.00E-29
32nm
45nm
65nm
1.00E-30
90nm
130nm
1.00E-31
1.00E-32
Optimal VT
0.85
0.8
0.75
0.7
0.65
0.6
0.55
0.5
0.45
0.4
32nm
45nm
65nm
90nm
130nm
Optimizing Total Leakage: Gate Replacement
9.4nA
• Minimize gate leakage by
using input vector control to
choose the optimal inputs.
18.9nA
5.7nA
• The total leakage is usually
concentrated in a few of the
gates.
• Replace those gates with
MTCMOS to further reduce
the subthreshold leakage in
those gates.
3.4nA
2.5nA
6.6nA
3.4nA
12.7nA
5.7nA
2.5nA
Optimizing Total Leakage: Results
Process
Size
Optimal Input
Mean
Leakage
Reduction
Mean Leakage
Reduction
(MTCMOS)
Mean Delay
Increase
130 nm
A=0000 0000 0000 0000
B=0000 0000 0000 0000
Cin=0
17.6%
28.9%
3.2%
90 nm
A=0000 0000 0000 0000
B=0000 0000 0000 0000
Cin=0
19.4%
30.4%
3.4%
65 nm
A=0000 0000 0000 0000
B=0000 0000 0000 0000
Cin=0
21.5%
33.9%
3.4%
45 nm
A=0000 0000 0000 0000
B=1010 1010 1010 1010
Cin=1
25.3%
41.8%
4.7%
32 nm
A=0000 0000 0000 0000
B=1010 1010 1010 1010
Cin=1
28.3%
45.2%
5.6%
Conclusions
• Gate leakage plays a significant role in leakage current as the
technology size is scaled down and it must be taken into account
when using leakage reduction techniques.
• Input vector control along with the use of stacking and threshold
voltage control can be used effectively to reduce both
subthreshold and gate leakage current.
• Heuristics can be extended to arbitrary circuits to optimize the
total leakage current.
• Further work can be done on sizing the transistors to improve
leakage current.
Questions?