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The M2 ASIC
A mixed analogue/digital ASIC for acquisition and control in data
handling systems
Olle Martinsson
AMICSA, October 2-3, 2006
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M2 summary
A mixed analogue/digital ASIC, including 32 kgates and a 12 bit
ADC, developed by Austrian Aerospace and Saab Space under an
ESA contract
Main application as generic core circuit for data handling I/O board
Controlled via OBDH bus or UART interface
Digital I/O functions include all common data handling system
interfaces, such as:
High level command pulse generation
Serial command and acquisition
Etc.
3.3V supply
Low power, typical consumption 12mW
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M2 block diagram
Configuration
Configuration
Config(1:0)
HlcStrN
UART /
OBDH
Bridge
BusAEn
BusBEn
OBDH
CTRL
RxAP
RxAN
Control
interface
RxBP
RxBN
TxAP
TxAN
TxAEn
TxAInh
CONFIG
AND
CMD
CTRL
RtAddr(4:0)
RtPar
Reset
RstAN
RstBN
Grp1Out(3:0)
IOGRP1
Grp1In
Grp2Out(3:0)
IOGRP2
Digital I/O
user interface
Grp2In
OBDH
RT
BUS
SEL
Ds
Port In
(DS16, Uart Rx,
Pulse Counter)
TxBP
TxBN
TxBEn
TxBInh
Address strap
ClkSync
Hlc
Port Out
ML
Bcp
Dac/Timer
UART Tx
Grp8Out(3:0)
IOGRP8
Grp8In
Mux Ctrl
&
Reset
ACQ
CTRL
Analog
VddAn
VssAn
ADC/
COMP
Buff
MUX
Clock detect
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VrefH
VrefL
Rref(3:0)
An(67:0)
ClkActive
Analog I/O
interfaces
M2 implementation
Commercial, epi-layered CMOS technology, AMIS 0.35µ with analog
options (double poly capacitors, high resistive poly resistors)
Radiation tolerant by “Rad hard by design”
Digital cell library developed within the project
Digital part designed using VHDL, logic synthesis and place & route
Chip size 25mm2
Prototypes via Europractice MPW in 160 pin CQFP package
Tested showing full functionality and full performance at first run
Implemented on a prototype I/O board for system level test, showing
similar or better performance compared to existing designs
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Rad hard by design
The methodology to reach radiation hardness has basically been the same for
analogue and digital parts. This includes:
Selection of submicron CMOS assures small threshold voltage drifts
NMOS edge leakage avoided by enclosed shaped transistors
Leakage between NMOS devices avoided by guard rings
Latchup avoided by guard rings and good substrate connections
SEU hardness achieved by means of resistive feedback in flip-flops
─ Limits maximum possible clock rate, but
+ Makes the design hard also to transients in combinatorial logic
Only low level measures, mainly on layout level, to achieve radiation hardness
 radiation aspects have only marginal impact on system, VHDL and
schematic level design
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Cell library design based on “shadow” library
M2 cells selected as a subset of and
compared with cells of a
commercially available “shadow”
library of a similar process
Cell library, just like analog parts
and top level design, developed
using a low cost PC based tool
from Tanner, including:
Tech
setup
Schematic
editor
Layout editor
TDB
DRC
(Design Rule
Checker)
Schematic
editor
Test bench
An. design
Spice
Spice Schematics
Extractor
Models
Spice
Analog
simulator
LVS
(Layout Versus
Schematic)
Schematic editor
Spice simulator
Layout editor
Cell
description
document
Design rule check
Extraction
Layout vs. schematic
Place & route
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M2 cell lib
Manual
comparison
Shadow
cell lib
Digital cell library
Library consists of:
3 flip-flops
14 combinatorial core cells
4 digital I/O cells
4 power I/O cells
Size of NAN2 gate 8.4 x 21 μm2, indicating 5.7 kgates/mm2
Size of NAN2 in AMIS library for the same technology, MTC45000:
4.5 x 12 μm2, indicating an area penalty factor 3.3 for the radiation
hardness
Gate density of the M2 after place & route = 31.7kgates / 15.7mm2 =
2.0 kgates/mm2 (only 3 metal layers used for place & route,
limitation by Tanner tools)
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Cell layout examples
MUX2
Output pad cell with tristate
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Digital design flow using the “shadow” library
VHDL tool
(text editor)
Digital part designed using a
standard flow including VHDL and
digital simulation
Logic synthesis performed using the
similar “shadow” library, but limited
to use only these cells that have
been implemented in the M2 library
Gate level simulation can be
performed using the shadow library
Backannotation (timing feedback
from layout) not possible, good
timing margins needed
Layout routing verified using netlist
from digital design, extraction of
layout and LVS
VHDL RTL
design
Digital simulator
Digital design
EDIF
Place&route and
chip level design
Analog
design TDB
M2 cell lib
Place &
Route
TDB
Layout editor
(digital and analog merge)
GDSII
DRC
(Design Rule
Checker)
TDB = Tanner layout
database format
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VHDL test
benches
VHDL
netlist
Logic
synthesizer
Shadow
cell lib
To foundry
9
VHDL tool
(text editor)
Netlist
conversion
Analog design
Spice netlist
Spice
Text editor
(digital and analog merge)
TDB
Top level
Spice
Extractor
Spice
LVS
(Layout Versus Schematic)
Analogue part description
ADC third order MASH ΣΔ type, 12.28 bits (4960 codes)
External 1.25V reference
Time discrete, switched capacitor based, operating at 500kHz (typical)
One conversion within minimum 100µs, including time for multiplexer settling
Buffered signal and reference inputs
66 channel input multiplexer
Digital outputs for control of external multiplexer
Switchable thermistor conditioning (for resistance measurements), giving:
Compact design (one conditioning resistor common for many channels)
High precision (minimum number of error sources)
Low power, only one channel powered at a time
Direct thermistor interface, no additional front-end needed
Includes comparator for binary acquisition of analog inputs (digital bilevel and digital
relay)
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Digital noise
Digital noise, which is a potential problem, especially substrate coupled,
was handled by:
Differential design
Topology (sigma-delta)
Separated digital and analogue supply lines
Input filter (especially considering unbalanced, non-differential inputs)
Early clock to analogue functions
Careful design of signal interfaces between digital to analogue
domains, e.g. filters are added where feasible
Careful package grounding, considering that grounds anyway are
connected via excessive substrate connections
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M2 layout
4921.5µ x 5028.5µ ≈ 24.75 mm2
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Test result summary
Power consumption typically 12mW, approximately 50/50 analogue/digital
Functional test OK
Analog performance:
ADC linearity measured to DNL < 0.17LSB and INL < 0.17LSB (1 sample)
Gain error: -0.8LSB average, 0.6LSB standard deviation (18 samples)
Offset error: -0.16LSB average, 0.14LSB standard deviation (18 samples)
Environment tested:
Supply voltage 2.8 to 3.6V
Temperature -30 to +85C
Total dose radiation up to 300krad and annealing
Heavy ion test up to 106MeV/mgcm2 effective LET
Life test, 1000 hours in +125C
ESD test up to 4kV HBM
Virtually radiation immune, both concerning total dose and heavy ions
No ESD damage up to 4kV HBM
Good stability considering:
Input common mode variations
Supply voltage variations
Temperature variations
Ageing
17 of 18 tested samples showed full function and performance (yield = 94%)
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Measured ADC linearity performance
DNL
1
0,8
0,6
0,4
0,2
-3000
-2000
-1000
0
-0,2 0
1000
2000
3000
1000
2000
3000
-0,4
-0,6
-0,8
-1
code
INL
1
0,8
0,6
0,4
0,2
-3000
-2000
-1000
0
-0,2 0
-0,4
-0,6
-0,8
-1
code
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DNL = Differential non-linearity
INL = Integrated non-linearity
Vertical scale in LSB
Measured ADC performance vs. temperature
GE
0
-40
-20
0
20
40
60
80
100
-0,5
M2#01
LSB
M2#15
-1
M2#16
M2#17
-1,5
M2#18
-2
degrC
OE
0
-40
-20
0
20
40
-0,1
60
80
100
M2#01
LSB
M2#15
-0,2
M2#16
M2#17
-0,3
M2#18
-0,4
degrC
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GE = Gain Error
OE = Offset Error
1 LSB = 0.5 mV
Measured ADC performance vs. supply voltage
GE
-0,9
-0,92 2,8
2,9
3
3,1
3,2
3,3
3,4
3,5
3,6
LSB
-0,94
-0,96
M2#01
-0,98
-1
-1,02
-1,04
Vsply
OE
0
2,8
2,9
3
3,1
3,2
3,3
3,4
3,5
3,6
LSB
-0,1
-0,2
M2#01
GE = Gain Error
-0,3
OE = Offset Error
-0,4
Vsply
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1 LSB = 0.5 mV
Measured ADC performance vs. life in 125C
1 LSB = 0.5 mV
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Measured ADC performance vs. total dose
1 LSB = 0.5 mV
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Measured supply current vs. total dose
IDDA (TID test)
1.80E-03
Ampere
1.75E-03
#01(ref)
#05
1.70E-03
#12
#13
1.65E-03
#14
1.60E-03
0
100
200
300
400 anealing
500168h
kRad
IDDI (TID test)
2.10E-03
Ampere
2.05E-03
#01(ref)
#05
2.00E-03
#12
#13
1.95E-03
#14
1.90E-03
0
100
200
kRad
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300
400anealing
500168h
IDDA = Analogue core supply
IDDI = Digital core supply
Note, step in IDDI was due to a
change in test setup (affected also
the reference M2)
M2 SEE test summary
Effective
TestRun Condition Vsply Temp SN#
LET
2
[V]
[ ºC ]
[#]
[MeV/mg·cm ]
2,8
RT
201
Static
06
30
2,8
RT
202
Static
07
30
2,8
RT
205
Static
07
60
3,6
85
206
Static
07
42,4
3,6
85
207
Static
07
75
3,6
85
208
Static
07
106
3,6
85
209
Static
06
106
2,8
RT
211
Static
06
106
2,8
RT
213
Static
07
106
2,8
RT
215
Static
07
106
2,8
RT
216
Dynamic
07
106
217
Static
2,8
RT
07
53
Fluence
2
[ p/cm ]
1,00E+06
3,02E+06
5,00E+06
5,02E+06
5,28E+06
1,02E+07
1,01E+07
1,02E+07
1,01E+07
1,00E+08
1,47E+07
1,01E+08
Equivalent SEL SEU Acq. Other
(1)
Fluence
errors events
2
[#]
[ p/cm ] [ # ] [ # ] [ # ]
2,00E+03
0
0
0
0
6,03E+03
0
0
0
0
9,99E+03
0
0
0
0
1,00E+04
0
0
0
0
1,05E+04
0
0
0
0
2,04E+04
0
0
0
0
2,02E+04
0
0
0
0
2,04E+04
0
0
0
0
1
2,02E+04
0
0
0
1
2,00E+05
0
0
0
2
2,76E+06
0
0
0
2,02E+05
0
0
0
0
Note 1: Equivalent fluence is applicable to Acquisition errors only.
Conclusion: The M2 is considered immune to heavy ions regarding SEL and
register SEU
Note: Maximum recorded acquisition error at LET=106 was 0.34% of full scale
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