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4/29/2017 840946415 1/11 The Common Source Amp with a Current Source VDD Now consider this NMOS amplifier using a current source. I * Note no resistors or vO(t) capacitors are present! Q1 * This is a common source amplifier. + _ vi(t) * ID stability is not a VG problem! Q: I don’t understand! Wouldn’t the small-signal circuit be: vo(t) =??? Q1 vi(t) + _ 4/29/2017 840946415 2/11 A: Remember, every real current source (as with every voltage source) has a source resistance ro . A more accurate current source model is therefore: ro I Ideally, ro = ¥ . However, for good current sources, this output resistance is large (e.g., ro = 100 KΩ ). Thus, we mostly ignore this value (i.e., approximate it as ro = ¥ ), but there are some circuits where this resistance makes quite a difference. VDD This is one of those circuits! ro I Therefore, a more accurate amplifier circuit schematic is: vO(t) Q1 vi(t) VG + _ 4/29/2017 840946415 3/11 And so the small-signal circuit becomes the familiar: ro vo(t) Q1 vi(t) + - Therefore, with the hybrid-pi model: id G1 D1 + vi + - vgs1 - vo gm v gs 1 ro 1 ro S1 Q: But, we implement a current source using a current mirror. What is the output resistance ro of a current mirror? A: Implementing a PMOS current mirror, we find that our amplifier circuit: 4/29/2017 840946415 4/11 VDD I vO(t) Q1 + _ vi(t) VG is specifically: VSS - Q3 - VSS VGS2 VGS3 + + Q2 vO(t) Iref Q4 Q1 vi (t) VG + _ 4/29/2017 840946415 5/11 Q: Yikes! Where did all those transistors come from? What is it that they do? A: Transistors Q2, Q3, and Q4 form the current mirror that acts as the current source. Note that transistor Q4 is an enhancement load—it acts as the resistor in the current mirror circuit. Note this amplifier circuit is entirely made of NMOS and PMOS transistors—we can “easily” implement this amplifier as an integrated circuit! Q: So again, what is the source resistance ro of this current source? A: Let’s determine the small-signal circuit for this integrated circuit amplifier and find out! Q: But there are four (count em’) transistors in this circuit, determining the small-signal circuit must take forever! A: Actually no. The important thing to realize when analyzing this circuit is that the gate-to-source voltage for transistors Q2, Q3, and Q4 are DC values! Q: ?? 4/29/2017 840946415 6/11 A: In other words, the small signal voltages v gs for each transistor are equal to zero: v gs 2 = v gs 3 = v gs 4 = 0 Q: But doesn’t the small-signal source vi (t ) create smallsignal voltages and currents throughout the amplifier? A: For some of the circuit yes, but for most of the circuit no! Note that for transistor Q1 there will be small-signal voltages v gs 1(t ) and vds 1(t ), along with id 1(t ). Likewise for transistor Q2, a small-signal voltage vds 2(t ) and current id 2(t ) will occur. VSS - VSS VGS 3 + 0 - VGS 2 + 0 + - + VDS 3 + 0 Q3 Q2 VDS 2 + vds 2 + + I ref + id + Iref + 0 + + + Q4 V + 0 DS 4 - VGS 4 + 0 - vO(t) vi (t) + _ Q1 VDS 1 + vds 1 - VGS 1 + v gs 1 - VG 4/29/2017 840946415 7/11 But, for the remainder of the voltages and currents in this circuit (e.g., VDS 4 , VGS 2 , ID 3 ), the small-signal component is zero! Q: But wait! How can there be a small-signal drain current id 2(t ) through transistor Q2 , without a corresponding smallsignal gate-to-source voltage v gs 2(t )? A: Transistor Q2, is the important device in this analysis. Note its gate-to-source voltage is a DC value (no small-signal component!), yet there must be (by KCL) a small-signal drain current id 2(t )! This is a case where we must consider the MOSFET output resistance ro 2 . The small-signal drain current for a PMOS device is: id 2 = gm 2 v gs 2 - vds 2 ro 2 Since v gs 2 = 0 , this equation simplifies to: id 2 = - vds 2 ro 2 4/29/2017 840946415 8/11 Equivalently, the small-signal PMOS model is: S2 - - vgs2 + G2 ro 2 vds2 + gm v gs D2 Thus for v gs 2 = 0 , the small-signal model becomes: S2 - - G2 ro 2 vds2 + vgs2 =0 + D2 Or, simplifying further: id S2 - ro 2 vds2 + id 2 = D2 vds 2 ro 2 id 4/29/2017 840946415 9/11 Thus, the small-signal model of the entire current mirror is simply the output resistance of the MOSFET Q2 ! ro 2 vo(t) Q1 vi (t) + - Comparing this to the earlier analysis--with a current source of output resistance ro : ro vo(t) Q1 vi(t) + - It is evident that the output resistance of the current mirror is simply equal to the output resistance of MOSFET Q2 !!!! ro = ro 2 4/29/2017 840946415 10/11 And so this circuit: VSS VSS Q2 Q3 vO(t) Iref Q4 Q1 + _ vi (t) VG VDD is equivalent to this circuit: Iref ro 2 vO(t) Q1 vi(t) VG + _ 1 Iref 4/29/2017 840946415 11/11 The resulting small-signal circuit of this amp is: vo + vi + - vgs1 - gm 1 v gs 1 ro 1 ro 2 And so the open-circuit voltage gain is: Avo = - gm 1 (ro 1 ro 2 ) = 2 K1 Iref (ro 1 ro 2 ) Note this result is far different (i.e., larger) than the result when using the enhancement load for RD: Avo K1 K2 However, we find that the output and input resistances of this amplifier are the same as with the enhancement load: Ri Ro ro 1 ro 2

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