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Chapter 10. Output stages and
power amplifiers
EMLAB
Contents
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1. Classification of output stages
2. Class A output stages
3. Class B output stages
4. Class AB output stages
5. Biasing the class AB circuit
6. CMOS class AB output stages
7. Power BJTs
8. Variations on the class AB configuration
9. IC power amplifiers
10. MOS power amplifiers
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Introduction
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1. 증폭기 output stage의 역할은 낮은 출력 임피던스를 제공하는 것.
2. 높은 전력 효율
3. Low distortion
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1. Classification of Output Stages
Conduction
angle (ϕ) = 360˚
180˚ < ϕ < 360˚
Conduction angle : 180˚
0˚ < ϕ < 180˚
Figure 10.1 Collector current waveforms for transistors operating in (a) class A, (b) class B, (c)
class AB, and (d) class C amplifier stages.
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2. Class A output stage
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Because of its low output resistance, the emitter follower is the most popular
class A output stage.
O   I   BE
Current source
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Class A output stage : voltages and currents
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I  VCC / RL
Figure 11.4 Maximum signal waveforms in the class A output stage of Fig. 11.2 under the
condition I = VCC / RL or, equivalently, RL = VCC / I. Note that the transistor saturation voltages
have been neglected.
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Class A : efficiency

Load power ( PL )
Supply power ( PS )
2
1 T
VCC
PL    L (t )iL (t )dt 
T 0
2 RL
2
2VCC
PS  2VCC I 
RL
I  VCC / RL
2
VCC
1
2 RL
 
  25%
2
2VCC 4
RL
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Example 10.1
Consider the emitter follower with VCC=10V, I = 100 mA, and RL= 100 Ω.
a. Find the power dissipated in Q1 and Q2 under quiescent
conditions
b. For a sinusoidal output voltage of maximum possible amplitude
(neglecting VCE,sat), find the average power dissipation in and
Also find the load power.
(a)
PD1  PD 2  VCC I  10  0.1  1[W ]
(b)
PD 2 
1 T
VCC I
[
V
sin

t

V
]
Idt

T  10  0.1  1[W ]
CC
CC
T 0
T
Vo2,rms (10 / 2 ) 2
PL 

 0.5[W ]
RL
100
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3. Class B output stage
Push-pull stage
Cross-over distortion
Figure 10.6 Transfer characteristic for the class B output stage
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Cross-over distortion
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Figure 10.7 Illustrating how the dead band in the class B transfer characteristic results
in crossover distortion.
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3.3 Power-Conversion Efficiency
2
VCC
P
2 RL 
 L 
  78.5%
2
PS 2VCC
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 RL
PL 
   VCC
Vˆo2
V2
 CC , Vˆo : peak output voltage
2 RL 2 RL
2
PS 
T

T /2
0
2
2VCC

TRL
iL 
VCC
sin  t
RL
2
2VCC
  (t )i (t ) dt 
TRL
 cos  t 
  
0
T /2

T /2
0
sin  tdt
2
2
4VCC
2VCC


 TRL  RL
 iL  (VCC  o  o )
o
RL
 VCC 
VCC
sin  t
RL
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3.4 Power Dissipation
PD  PS  PL
2 Vˆo
1 Vˆo2
PD 
V 
 RL CC 2 RL
PD 2 VCC Vˆo


Vˆo  RL RL
 PD ,max
2
2VCC
 2
 RL
 Vˆo
PD , max

2

 PDN ,max  PDP ,max
VCC
2
VCC
 2
 RL
Figure 10.8 Power dissipation of the class B output
stage versus amplitude of the output sinusoid.
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Example 10.2
It is required to design a class B output stage to deliver an average power of 20 W to an 8-Ω load.
The power supply is to be selected such that VCC is about 5 V greater than the peak output voltage.
Determine the supply voltage required, the peak current drawn from each supply, the total supply
power, and the power-conversion efficiency. Also determine the maximum power that each
transistor must be able to dissipate safely.
PL 
Vˆo2
 20 [W ]
2 RL
Vˆo  2 PL RL  2  20  8  17.9[V ]
VCC  Vˆo  5  23[V ]
ˆ
ˆI o  Vo  17.9  2.24[ A]
RL
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PS   PS  

1

 2.24  23  16.4[W ]
PL
20

 100  61%
PS 32.8
PDN ,max  PDP ,max
2
VCC
( 23) 2
 2  2
 6.7[W ]
 RL   8
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3.5 Reducing Crossover Distortion
Figure 10.9 Class B circuit with an op amp
connected in a negative-feedback loop to reduce
crossover distortion.
3.6 Single-Supply Operation
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4. Class AB Output Stage
VBB에 의해 동작점
의 DC 바이어스 전
류가 정해짐
iN  iP  I Q  I S eVBB / 2VT

 BEN
i N  iP  iL
O   I 


 EBP

VBB
  BEN
2
 BEN   EBP  VBB
VT ln
I
iN
i
 VT ln P  2VT ln Q
IS
IS
IS
 iN iP  I Q2
i N  iP  iL
 iN2  iN iP  iLiN
 iL  i N 
 iLiN  iN2  I Q2
I Q2
iN
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4.2 Output Resistance
Rout  reN || reP
reN 
VT
V
, reP  T
iN
iP
 Rout 
VT VT
VT

i N iP i N  iP
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5.1 Biasing Using Diodes
•
VBB는 IBIAS에 의해 정해진다.
•
D1, D2는 QN, QP에 비해 작아도 된다.
•
그러나 부하 전류가 증가함에 따라 QN, QP
의 base 전류도 증가하는데 이를 IBIAS가 공
급하려면 이 전류는 어느 크기 이상이어야
한다.
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즉 다이오드 전류가 어느 정도 커져야하는
점이 다이오드 바이어싱의 단점이다.
•
전류가 증가할 때 thermal runaway를 막는
것은 장점이다.
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Example 10.4
Class AB output stage의 Vcc=15V, RL= 100Ω이다. 이 때 출력 전압은 진폭이 10V인
사인파이다. 두 트랜지스터 QN, QP는 matched pair이고 Is=10-13A, β=50이다. 바이
어스용의 다이오드는 두 트랜지스터 면적의 1/3이다. 다이오드에 흐르는 전류가
항상 1mA보다 크게 하는 Ibias를 정하시오. Output stage의 트랜지스터 동작점의
전류와 소모 전력을 구하시오. 출력 전압이 0, 10, -10V일 때 VBB를 구하시오.
iL,max 
10
 100mA
0.1k
iB 
iL,max

 2mA
I BIAS  1m  iB ,max  3mA
I C  3I BIAS  9mA
PDQ  2  15  9  270mW
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I S ,diode   1013 A
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Vo= 0V 일 때,
iB 
9
 0.18mA
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VBB  2VT ln
iD  I BIAS  iB  3  0.18  2.82mA
2.82m
 1.26[V ]
I S ,diode
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5.2 Biasing Using the VBE Multiplier
I C1  I BIAS  I R
IR 
VBE1
R1
 R 
VBB  I R ( R1  R2 )  VBE1 1  2 
R1 

VBE1  VT ln
I C1
IS
Figure 10.15 A class AB output stage utilizing a VBE multiplier for biasing.
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