Download the bitscope design

THE BITSCOPE DESIGN
Browse this part of the website to learn about:
1.
What Bitscope is, how it works, and how to use it.
2.
The hardware design schematics, fully annotated.
3.
How to program Bitscope (including a detailed manual).
4.
What parts you need to build a Bitscope.
5.
Some free software you can download for Bitscope.
The key features of the BitScope design are:

Simultaneous analog/digital capture

100 MHz sub-sampling bandwidth

50 Ms/s logic sample rate (max)

40 Ms/s analog sample rate (max)

20 MHz single-shot bandwidth

4 analog inputs (multiplexed)

Fully
programmable
using
ASCII
"scripts"

Simple
virtual
machine
programming

Optional A/D convertor modules

Expansion POD for external devices

Low cost PIC 16F628 design
o
2 inputs via BNC (buffered 1Meg)

All logic in a single PLD
o
2 inputs via DB25 POD

115 kb/s Serial Interface or

625

8 logic inputs via DB25 POD

Two 32K x 8 capture buffers

Sophisticated triggers (analog or digital)

1.25 Mb/s USB Interface

10 MHz arbitrary waveform generator

"Atomic" ASCII command set

Scalable design to >100MS/s @ 3.3V

Chipset suitable for embedded DSO
kb/s
10BaseT
Ethernet
Interface
Hardware Design
This section describes the original hardware. The BS300
design is similar. BS300 schematics are available here.
The schematics below describe the main circuit.
If you have a PDF reader installed in
your web browser, you can click on
the thumbnails to see each
The next few pages walk you through the design.
The sub-sections provide details of the analog circuits, A/D
convertor and expansion POD.
schematic in detail.
You can also can download all five
sheets in one zip file from our
download area.
This is the master Bitscope schematic.
All the following sheets show parts of
In addition to the main circuit, you
this circuit in greater detail.
can also view the schematics of our
Sheet 1
high speed A/D convertor.
Power supply and serial interface
circuits.
A/D Convertor
Sheet 2
and our new circuit prototyping
system called Proto POD
Logic Analyzer circuit.
Sheet 3
Proto POD
Sheet 4
Analog inputs, buffers and A/D
which connects to Bitscope's Logic
convertor interface.
POD connector.
Vertical input channel buffer amplifiers.
Sheet 5
Main Board
Analog Inputs
The primary source of analog signals is through the CH A and CH B BNC connectors.
These input circuits are designed to be compatible with normal 10:1 CRO probes.
This schematic left shows CH A. CH B is identical.
S1 provides AC/DC coupling via 100nF cap C32 and the 1M resistor to GND provides the nominal
1M input impedance.
R25, C31, D8 and D9 and provide input protection.
The high impedance voltage follower circuit use JFETs Q6 and Q7.
The Opperating point and offset adjust is set by Q3/RV3.
MAXIM to the rescue
JFETs have quite a high output impedance so U23, a unity gain follower, is provided to buffer the
analog signal to the next stage.
Of course, this buffer and others that follow it must perform to the highest standards if the integrity
of the analog signal is to maintained until it reaches the A/D convertor.
A few years ago, wide bandwidth OP Amps were considered rocket science. Then came the Maxim
MAX477. This device has a 300 MHz GBP, uses voltage feedback and is happy to drive 50 ohm
capacitive loads. As an added bonus, it
has a 1 Meg input impedance and
negligible input capacitance.
This is just the ticket for getting a wide
bandwidth signal to an A/D convertor.
The analog path to the A/D convertor passes through a
series of these wide bandwidth OP amps before being
applied to 4:1 analog multiplexer. This combination
avoids RC filters which could degrade the high
frequency components of our signal.
Logic POD Analog Inputs
The other analog inputs connect via the POD and are
attenuated by the 20K network R22 and R23.
The schematic left shows CH B. CH A is identical.
To compensate for the input capacitance of the
multiplexer which follows this circuit, an optional speedup capacitor C57 is available. This may
need to be trimmed and should have a nominal value of Cin/4 (about 0-10pF).
The maximum input voltage of the range buffer which follow this is ±3V. So given an attenuation
factor of 4.830, this means a maximum analog voltage at the POD of ±15V can be measured. This
is suitable for most solid state designs. Higher voltage ranges can be accomodated with extra
circuitry in the POD itself.
Analog Input Multiplexer
The 4 input buffers feed a MAX4052 MUX to select one of them to pass on to the next stage.
U17 selects the input according to the values of:
(1) PIC pin RA2: CH-A/B select and,
(2) PLD pin PG0: BNC/Pod select.
CH-A/B is under the control of the PIC which can be programmed to chop the source between the
pair of BNC inputs or the pair of POD inputs during a trace.
BNC/Pod is set via an option bit in Spock and may only be changed when Spock is reloaded. That
is, between traces.
This signal also selects the SRAM bank so we have a completely separate 16K buffer for both
Analog and Digital samples for POD and BNC sources !
As a bonus, there is a spare 4:1 MUX in U17 used to activate 1 of 4 front panel LEDs
Channel sample indicators on the front panel such as these are
an important feature of
modern DSO :-)
They look good and tell you when Bitscope is actually
acquiring analog data.
Range Buffer
U14 is a straight 300 MHz unity gain follower that buffers the
output of the multiplexer. The low impedance output of this
buffer drives the attenuator section. 3 Resistor networks
give attenuation of 1, 2 and 5.273. The other option is a x
4.583 gain stage to boost low level signals.
The 4 range options are switched by MUX U18 (4052). This
MUX is addressed by RNG0, RNG1 outputs from the PIC.
Depending on the 4052 (MAXIM is best) you may need to add a small speedup cap C69 to the 5:1
range for ideal frequency response. A poor mans trimmer can be made from some adhesive copper
foil (stained glass supplier) and a bit of paper.
Gain Buffer
U15 is configured as a (x 4.583)
non-inverting amp to boost small
signals to feed the ADC. It is possible
to use the MAXIM 477 device here,
but for a gain of 5 it has only a
bandwidth of 25 MHz. The better
choice is the Analog devices AD8048
which is optimized for gains of +2 or
more.
At a gain of 5, the AD8048 has a
bandwidth of better than 50 MHz. For
even better performance you may be
able to reduce the gain of U15 slightly.
The bandwidth improvement will
follow 1/[1+Rf/Rg]. The
AD8048 has a unity gain
mate - the AD8047 - which is
virtually a drop in
replacement for the MAXIM
477.
If you use the Analog
Devices AD9057 ADC (the
pick of the litter) which has a
1 V span, you may halve the
gain of this stage, preserving
the 100MHz bandwidth
across all ranges. This is
useful, even though the
AD9057 samples at
40/60/80 MSPS it has an
analog bandwidth of 120MHz!
This may seem confusing,
but will be explained below.
There is a bit more to
sampling than you might
think.
By the way, because this is a
8 bit sample engine, we
don't care too much for
whole numbers in the gains.
The Host display software can sort this out with high precision arithmetic. All the Host needs to
know are the constants for each range for a device. There lies a use for some of the 64 bytes of
EEPROM in the PIC16F84!
ADC Buffer
After the range selector the analog signal is buffered and amplified by U16.
This stage has a gain of 1.667 which takes an input clamped at ±0.6v and outputs a ±1.0v signal.
The output offset is set by emitter follower Q5 and RV1. Adjusting RV1 will shift the signal span to
match the input of the A/D module
being used.
For example:
(1) The Motorola ADC has a 2V span
centered at 1V.
(2) The AD9057 has a 1V span
centered at 2.5V
(3) The TI TLC5540 has a 2V span
centered at 1.62V
Diode clamps on the input to U16
ensure that the input to the ADC never
exceeds 2V p-p.
Some ADC chips do not tolerate overvoltage on the input.
Current limiting resistors R38, R29 ensure that the mighty MAXIM drivers do not exceed the
current limits of the Range Select multiplexer.
The ADC Buffer provides a low impedance drive for the ADC, which may be a few hundred ohms
and 30 pF or so. Note that C27 takes off the AC component of the input to the ADC for edge
counting in Spock.
RV2 is connected to pin 24 of the ADC to adjust the span. This allows the span to be calibrated if
possible for the particular ADC in use.
A/D Interface
Bitscope's modular A/D interface allows the use of more than one type of A/D convertor.
The interface itself is simple.
The data bus drives the Analog SRAM, Spock and MUX. The sample clock is the same zz-clk used
by Spock and !STORE drives the !OE pin.
The "nominal" A/D convertor for Bitscope is the now obsolete Motorola MC10319 "Flash
Convertor" which used a comparator tree and gray scale decoder allowing it to be clocked from
25MHz down to DC.
When Bitscope was designed, this A/D convertor was already "on its way out", so why design in an
outdated chip ?
Because it's the perfect
footprint for a replaceable A/D
Module !
The MC10319 was available in a
24pin 600mil package. It used
all the analog and digital power
supplies, data bus, and control
signals as required by any A/D
convertor.
Rather than design a new PCB
for every different ADC chip on
the market (which are all
surface mount now anyway) it seemed a better bet to design for the Motorola part, then make a
24pin 600mil "carrier" PCB for each new Flash ADC of interest.
If you examine the spec sheets on a many A/D convertors, you will see they work in much the same
way. The only real difference is the input offset and span details.
The module scheme adopted in Bitscope is quite flexible. It is even conceivable that a 16 bit ADC
module could be devised that outputs odd/even byte pairs.
PIC Processor
Bitscope is based on the MicroChip PIC 16F84.
The PIC's fast RISC instruction set and the tri-state I/O pins make it ideal for Bitscope.
At first glance you may think that an 18 pin PIC does not have enough pins for a useful design.
However, with careful planning it is possible to use most pins for more than one function which
makes good use of the features of this innovative microcontroller while keeping the construction
costs down.
The key is to reuse several of the pins depending on the hardware operating mode. In Bitscope's
case, two modes are defined; COUNT and SHIFT.
Here is a brief description of the pin functions:
PIN
Function
Description
COUNT mode:
RA0
Range 0
RA1
Range 1
Output pins that control the Analog gain of the Y amplifiers.

0 Gain = 4.583

1 Gain = 1.000

2 Gain = 0.500

3 Gain = 0.190
Note that the gain of the ADC Buffer is 1.667
SHIFT mode:
POD I/O 0
I/O pins that are available at the LOGIC POD for external Smart
POD I/O 1
PODs. In COUNT mode, analog switches isolate these signals from
the LOGIC POD.
Output pin that swiches the Analog source between CHA BNC and
RA2
Channel A/B
CHB BNC, or in POD mode between PODA or PODB analog signals
brought from the LOGIC POD.
"The clock that sleeps". Tri-state I/O pin. State machines in PLD
devices should not be exposed to glitches on the clock. Some
registers may see the clock, others may may not, resulting in
non-deterministic behavior. Jamming a 50MHz clock signal is not
RA3
zz-clk
polite. U6A (74AC74) is double clocked by frequency doubler U3D
(74AC86) (on the clean edge) and allows the PIC to have 3 state
synchronous control via RA3. High, Low, Freerunning - no glitches.
This control is important as we must use zz-clk to shift in control
words to the PLD as well as modulate the sampling for lower
frequency timebase measurements.
Input connects to U5 8:1 MUX to read the 8 data bits of the Logic
RA4
Digital Data
Analyzer RAM bus. Bit7 is routed through Spock to be optionally the
TRIGGER MATCH or FREQUENCY/EVENT signals. RA4 may be
connected to the PIC prescaler in the OPTION register
COUNT mode:
Input connects to U4 8:1 MUX to read the 8 data bits of the ADC RAM
RB0
Analog Data
Bus. As RB0 is the PIC INT source, during SAMPLE, if the MUX points
to Bit7 then INT may be used as a zero crossing detector for Analog
TRIGGER (in additional to the Complex trigger implemented in the
PLD)
SHIFT mode:
Spock Data In
Output signal is Shift-In data to feed Spock which needs 5 bytes to
set up counters, trigger bytes and options.
RB1
SEL 0
COUNT mode:
Output A0 for data MUXs U4, U5.
SHIFT mode:
Spock Data Out
Input Shift-Out data from Spock. Current 16 bit counter state in
Spock is shifted out as new data is shifted in.
RB2
SEL 1
RB3
SEL 2
Output pins A1, A2 for data MUXs U4, U5.
Output which controls the hardware mode. That is, COUNT or SHIFT.
RB4
COUNT/!SHIFT
A value of ONE causes Spock to shift new data into its registers. A
value of zero causes Spock to count and trigger.
RB5
Serial Out
Serial data output.
RB6
Serial In
Serial data Input.
Output control for RAM and ADC/Buffer control. This signal selects
RB7
STORE/!READ
either read or write for the RAM, allowing SAMPLE data written to
RAM, or later read back.
CLKI
CLKO
Clock Select
The PIC is clocked by a crystal - which depending on the PIC device
may be 4MHz, 10 MHz or 20MHz
Spock PLD
Bitscope uses a Lattice PLSI1016 PLD (Spock) to implement the data capture engine.
Spock "soaks up" a lot of logic and makes the circuit look much simpler than it really is. It
implements the equivalent of 16 to 20 medium density TTL devices.
Spock performs two functions:
(1) Address generation for the SRAM capture buffers, and
(2) 8 bit pattern matching for trigger
generation.
It is driven by the zz-clk signal and
operates in one of two modes:
COUNT mode (RB4 low): counter
enabled and comparator monitoring
the byte stream for trigger matches.
SHIFT mode (RB4 high): counter
shifting in bits from A-DATA (RB0),
and shifting out bits to SEL0 (RB1).
We can reload the counter and find
out where it was up to when we
stopped it. Bits from the top of the counter are also shifted up to the comparator circuits to load the
trigger.
Spock is connected to the three internal busses in Bitscope:
BUS
Name
A13/A0
Address
DD7/DD0
Digital Data
AD7/AD0
Analog Data
Description
The 14 bit address bus. Spock drives this bus when capturing
data.
Data from the Logic POD is read into Spock during a capture
trace for use by the trigger logic inside Spock.
Data from the A/D convertor is read into Spock during a capture
trace for use by the trigger logic inside Spock.
Full details of Spock's functional operation are available here.
The Capture Engine (Spock)
The Bitscope PLD (Spock) is the data capture chip.
Spock implements the high speed data capture logic that captures both analog and digital data to
the dual paged SRAM buffers.
It manages buffer pages, the sample capture address and BNC/POD source selection. It selects
which inputs to capture, their attenuation, and executes the trigger logic that decides when a
trace should complete.
Spock is controlled by a set of control and counter registers:
Spock Control Registers.
R3
Sample Pre-load (Low Byte) Spock Counter/RAM address (low byte).
R4
Sample Pre-load (High Byte) Spock Counter/RAM address (high byte).
R5
Trigger Logic Byte
Logic values to match for trigger.
R6
Trigger Mask Byte
Don't care logic values for trigger.
R7
Spock Option Byte
Trigger and PG1 setup in Spock.
Spock Counter Registers.
R9
Counter Capture (Low Byte) Spock Counter/RAM address capture (low byte).
R10 Counter Capture (High Byte) Spock Counter/RAM address capture (high byte).
R14 Input/Attenuation
Alt/Chop channel input/attenuation settings.
R15 Dump Size
Number of samples dumped per request.
Two commands move data between these registers in the virtual machine and Spock itself:
>
0x3E
Download Spock Control Registers R3..R7.
<
0x3C
Capture Spock Counter Registers to R9..R10.
Prior to starting a trace (T), the Spock registers must be downloaded to Spock using the >
command. However, Spock registers themselves need only be programmed once if their value
does not need to change between successive traces.
After a trace completes, the 16 bit sample address counter maintained by Spock is returned to the
host automatically. It may also be read from the Spock counter registers after a issuing <
command to read its value from Spock.
The following pages describe the programming of the Spock Registers R3..R7 the use of the Spock
Counter Registers R9..R10, the programming of the capture trigger logic and the selection of
signal inputs and attenuation ranges via register R14.
The Spock Option Byte (R7)
Spock's operation is defined by the Option Byte R7 which has 6 control bits:
Bit
5
4
3
2/1
0
Name
Trigger Type
Edge Direction
Page Selection
Trig Bit 7 MUX
Trigger Source
Value
Meaning
0
Trigger operation is Level Sensitive.
1
Trigger operation is Edge Sensitive.
0
Trigger asserted on FALSE -> TRUE
1
Trigger asserted on TRUE -> FALSE
0
Lower 16K RAM Page and Analog BNC Input.
1
Upper 16K RAM Page and Analog POD Input.
0
DD7 : Digital Data Bus Bit 7.
1
Comparator : trigger match comparator signal.
2
Event 1 : (Pre-scaler output frequency halved).
3
Event 2 : (ADC input frequency halved).
0
Digital trigger source.
1
Analog trigger source.
Bits 6 and 7 are reserved and should be programmed with zero for compatibility with future Spock
revisions. All these bits must be programmed before each data capture trace.
The following pages describe these bits and other Spock registers in more detail.
Buffer Page and POD Selection (R7:3)
Analog and digital data are captured simultaneously to two separate 32K RAM buffers.
Each buffer is divided into two 16K pages.
Bit R7:3 selects which of these pages in both buffers are to be used for data capture:
Bit
3
Name
Page Selection
3
POD Selection
Value
Meaning
0
Lower 16K RAM Buffer Page.
1
Upper 16K RAM Buffer Page.
0
Analog via BNC Inputs.
1
Analog via POD Inputs.
As you can see from the table, the same bit also selects which of the two sets of analog inputs are
to be applied to the A/D convertor. Signals available at the BNC inputs may be captured to the
lower bank and signals available at the POD inputs may be captured to the upper bank only.
Of course digital signals are available at the POD only and may be captured to either bank.
Input/Attenuation Selection (R14)
The Input/Attenuation Register R14 selects which analog input (A or B) will be captured and what
amount of attenuation will be applied before A/D conversion.
Four bits are used to program these features:
Bit
1/0
2
3
Name
Attenuation Range
Channel Select
zz-clk Level
Value
Meaning
0
Attenuation Range 1.
1
Attenuation Range 2.
2
Attenuation Range 3.
3
Attenuation Range 4.
0
Input from channel B.
1
Input from Channel A.
0
Always set to one.
There are two sets of these bits, one in each of the upper and lower nybbles of R14.
One or both sets may need to be programmed depending on the selected trace mode.
Recall that there are two pairs of A/B analog inputs, one pair via the BNC connectors on the front
panel, the other pair via the POD. The attenuation actually applied depends on which inputs are
used, and if BNC, whether a x10 probe is connected:
Attenuation Range
BNC x1
BNC x10
POD
1
±130mV
±1.30V
±632mV
2
±600mV
±6.00V
±2.90V
3
±1.20V
±12.0V
±5.80V
4
±3.16V
±31.60V
±15.80V
The Trigger (R5,R6,R7)
During a trace, Bitscope "marks" the data when a trigger event occurs.
The trigger is programmed to tell Bitscope under what conditions the trigger event should occur.
Programming the trigger requires:
1.
Source selection (Analog or Digital).
2.
Logic definition (High, Low, Don't Care).
3.
Analog type selection (Level or Edge).
The third step is of course required only if an analog trigger is selected.
Trigger Source (R7)
Three bits R7:0 and R7:2/1 are used to select the trigger source:
Bit
0
2/1
Name
Trigger Source
Trigger Bit 7
Value
Meaning
0
Digital trigger source.
1
Analog trigger source.
0
DD7 : Digital Data Bus Bit 7.
1
Comparator : trigger match comparator signal.
2
Event 1 : (Pre-scaler output halved).
3
Event 2 : (ADC input halved).
When the Trigger Source is digital, the trigger is calculated using the 8 logic analyzer channels
directly. When it is analog, the trigger is calculated using the 8 bit data from the A/D convertor.
Trigger Bit 7 must be set to Comparator for the selected Trigger Source to be used. The other
choices are used for period measurement and other specialized functions which are described
elsewhere.
Trigger Logic (R5,R6)
The trigger is expressed as an 8 bit ternary number which is compared with the 8 logic analyzer
channels or the 8 bit digitized analog signal. These bits express whether the trigger is to occur on
a HIGH (1), LOW (0) or DON'T CARE (X) condition for each bit.
For example, a trigger on bits 0, 3, and 5 HIGH and bits 2 and 4 LOW with DON'T CARE for the rest
is expressed as:
Trigger Condition = XX1010X1
The two trigger logic registers programmed together define this trigger condition:
R5
Trigger Logic Byte
Logic values to match for trigger.
R6
Trigger Mask Byte
Don't care logic values for trigger.
The example trigger condition above could be programmed as:
R5 <- 00101001
R6 <- 11000010
where a HIGH (1) values in the Trigger Mask register R6 mean DON'T CARE regardless of the
values in the corresponding bits in the Trigger Logic register R5.
Analog Triggers (R7)
When triggering on analog signals in any trace mode other than zero, the trigger registers are
augmented with bits 4 and 5 of the Option Byte R7:
Bit
5
4
Name
Trigger Type
Edge Direction
Value
Meaning
0
Trigger operation is Level Sensitive.
1
Trigger operation is Edge Sensitive.
0
Trigger asserted on FALSE -> TRUE
1
Trigger asserted on TRUE -> FALSE
To implement triggering on an analog signal zero crossing the trigger logic registers should be
programmed as:
R5 <- 00000000
R6 <- 01111111
and R7:5 asserted for edge trigger operation. The value of R7:4 then determines whether the
trigger occurs as the signal moves from negative to positive or vice versa.
By programming different values for R5 and R6 analog signal levels other than zero may be
programmed. It is even possible to program multiple signal level bands for the analog trigger using
DON'T CARE logic. Note that in trace mode zero, edge triggers do not apply and the values of these
control bits are ignored.
Sample Address Counter (R3/4/9/10)
Spock maintains a 16 bit counter to track the current sample address in capture RAM during a trace.
The counter stops at the end of a trace and its value used for data upload.
The Sample Pre-load registers are used to program the sample address from which Spock should
start counting when a trace is enabled. Usually these will be programmed to be zero but can be any
16 bit value:
R3 Sample Pre-load (Low Byte)
Spock Counter/RAM address (low byte).
R4 Sample Pre-load (High Byte)
Spock Counter/RAM address (high byte).
Note the address range of the RAM page to which data may be captured is 14 bits. That is, the 16
bit counter cycles through a page 4 times before it wraps. This may seem redundant, but is in fact
useful when the counter is used for frequency or period measurement purposes.
The Sample Capture registers contain the Spock sample address after a trace has completed
following the assertion of the trigger and the execution of the Capture Spock Counter command <:
R9
Counter Capture (Low Byte)
R10 Counter Capture (High Byte)
Spock Counter/RAM address capture (low byte).
Spock Counter/RAM address capture (high byte).
It will usually be most convenient to use the value of the Sample Address Counter returned
automatically upon completion of Trace command instead of updating and reading the R9, R10
registers. The counter value is returned as a string of 6 characters:
<CR> <H3> <H2> <H1> <H0> <CR>
where <H?> are the 4 hex digits of the 16 bit counter value.
Retrieving Data (R15)
Captured data may be retrieved with one of three dump commands:
S 0x53 Sample dump (CSV format, analogue & digital data).
M 0x4D Mixed memory dump (Binary format, analogue & digital data).
A 0x41 Analog memory dump (Binary format, analogue data).
Each time one of these commands is issued, a finite set of samples is dumped to the host via the
serial port. The first dump (after a trace completes) starts at the last recorded sample address.
Each subsequent dump continues where the previous one left off allowing the entire contents of
capture memory to be uploaded to the host using multiple dump commands.
The size of each dump is determined by the values programmed to the Dump Size register R15
which ranges from 1 to 256 samples (the value 0 implies 256). The dump size should not be larger
than the number of samples the host can accept in one hit without hardware handshake.
The format of the dumped data depends on the dump command used:
S
=> <CR>DDAA,DDAA,DDAA,DDAA ... DDAA<CR>
DD is an 8 bit digital/logic sample, and
AA is an 8 bit analogue sample.
Both are ASCII encoded as a pair of hex characters.
M => dadadadadada ... da
d is an 8 bit digital/logic sample, and
a is an 8 bit analogue sample.
Both are binary encoded as a single byte each.
A
=> aaaaaaaaaaa ... a
a is an 8 bit analog sample binary encoded.
If suitable pre and post trigger delays are programmed, the capture buffers will be completely filled.
By reading from the sample address at which capture stopped, and issuing the required number of
dump commands, a contiguous dump from the first captured sample to the last can be uploaded to
the host without reference to the sample address at all.
If less than a full buffer has been recorded, it is of course possible to program the sample address
counter to start the first dump at any sample address regardless of where the most recent trace left
off.
Trace Modes
Bitscope performs data capture according to a selected trace mode.
The trace mode controls how many analog channels to capture and what type of timebase to
use. It also applies an optional pre and/or post trigger delay to allow data before and/or after to
trigger to be captured.
Five registers are used to program the trace mode:
R8
Trace Register
Trace mode selection.
R11
Post Trigger Delay
Delay after trigger (low byte).
R12
Post Trigger Delay
Delay after trigger (high byte).
R13
Time-base Expansion
Time-base expansion factor.
R20
Pre-Trigger Delay
Buffer prefill before trigger.
The most important trace mode register is the Trace Register R8. The low 4 bits of this register are
programmed to with a Trace ID to select one of 6 available modes:
ID
Mode
Channels
Trigger
TM0
Simple Trace Mode
Single Channel
Level Trigger.
TM1
Simple Trace Mode
Dual Channel (Chop)
Enhanced Trigger.
TM2
Time-base Expansion
Single Channel
Enhanced Trigger.
TM3
Time-base Expansion
Dual Channel (Chop)
Enhanced Trigger.
TM4
Slow Clock Mode
Dual Channel (Chop)
Enhanced Trigger.
TM8
Frequency Measurement
N/A
N/A
The values to program to the other trace mode registers depend on the selected mode. Also, the
upper 4 bits of the Trace Register R8 are reserved and should always be programmed as zero.
Pre/Post Trigger Delays (R11,R12,R20)
All trace modes (except zero) step through 3 states during a trace:
State
Name
Description
The period of time during which Bitscope captures data
without enabling the trigger. The duration of this state
1
Pre Trigger Delay
depends on the value in the Pre-Trigger Delay R20.
It is used to ensure Bitscope captures a minimum amount
of data before a trigger event.
After expiry of the Pre Trigger Delay, Bitscope continues to
2
Trigger Enabled
capture data, but now the trigger is enabled.
It stays in this state until a trigger is seen.
Upon the assertion of the trigger condition, Bitscope
enters the Post Trigger Delay state where is continues to
capture data for an additional period of time which
3
Post Trigger Delay
depends on the value in the Post Trigger Delay R11, R12.
It is used to ensure that Bitscope captures a minimum of
amount of data after a trigger event.
By programming appropriate pre and post trigger delays (which apply in states 1 and 3), it is
possible to capture analog and digital data before and/or (well) after the trigger event.
Slow Clock/Time-base Expansion (R13)
Bitscope normally acquires data at 25 MS/s or 40 MS/s
However, sometimes such a high capture rate is not what you want.
Trace modes TM2 and TM3 use time-base expansion and trace mode TM4 slow clock operation to
allow the effective sample rate to be reduced for those applications that may require a low sample
rate to capture signals of lower bandwidth data over a longer period of time.
The time-base expansion trace modes 2 and 3 use the Time-base Expansion Register R13 to slow
data capture by inserting a repeating pause state during data acquisition. The captured data
therefore consists of a series of small sample data sets which are actually sampled at full speed (ie,
the A/D convertor still operates at 25 or 40 MS/s).
The average of the sample sets defines the sample value at the expanded (ie, slower) rate.
The advantage of time-base expanded data capture is that high frequency statistics (such as short
term jitter or noise) can be determined from the same sample set.
If you are not interested in the high frequency statistics, you can use the Slow clock trace mode as
an alternative to time-base expansion. Slow clock mode uses the same register R13 to actually
slow the sample clock used by the A/D convertor and as such requires that the convertor you're
using can be clocked at the lower rate.
In the case of the Motorola MC10319 the sample clock may be driven to very low sample rates. The
lowest sample rate supported in slow clock mode is 3 kHz which allows the continuous capture of
up to 5 seconds of data.
Dual Channel Operation
Trace modes TM1, TM3 and TM4 can be set up to capture data from two inputs.
About Trace Channels...
Bitscope has one A/D convertor but 2 trace channels; one called primary, the other secondary.
Trace channels are key to dual channel operation. They control the input selection and
attenuation for each channel of analog data that is recorded.
Register R14 contains two sets of control bits; one for the primary, the other for the secondary.
The settings are independent of each other; they can even be set the same.
Trace modes TM0 and TM2 capture data using the primary channel only. Modes TM1, TM3 and
TM4 use both channels. All modes trigger on the primary channel only.
Dual Channel (ALT)
Trace mode TM1 captures two inputs using a technique similar to ALT MODE on an analog
oscilloscope. It allows both channels to captured relative to a trigger event occuring on the primary
channel.
When both analog inputs are connected to phase related periodic waveforms, it is possible to
capture continuous segments from each while maintaining their phase relationship.
TM1 allows Bitscope to capture a buffer from the primary channel and then one from the
secondary channel, both referenced to the same trigger event, for subsequent display together.
Dual Channel (CHOP)
Of course, your analog oscilloscope also has CHOP MODE to show two channels, and so does
Bitscope.
In this case, trace modes TM3 and TM4 support channel chopped data capture. That is, the
primary and secondary trace channel are swapped repeatedly after a trigger event on the primary
channel, so the captured data contains a series of alternating sample sets from the primary and
secondary channels.
Normally each trace channel will be programmed for a different input and/or attenuation range, as
approprate for the system under test.
However, it is of course also possible to program both the primary and secondary channels with the
same settings, in which case channel chop reverts to single channel capture. Use this technique if
you want to capture one channel with a slow clock.
Sample Skew
Bitscope is a mixed mode device which captures both digital and analogue data. When analyzing
mixed mode captured data it is important to take account of the analog sample skew (ie, time
delay) associated with the A/D convertor to ensure its alignment with the digital data.
The sample delays associated with the digital inputs and various A/D convertors that can be used
with BitScope are:
Digital/Logic Inputs
0.5 samples
Motorola MC10319 ADC
1.5 samples
Exar 8786 ADC
4.5 samples
Analog Devices AD9057
4.0 samples
Texas Instruments TLC5540
4.0 samples
Note also in all trace modes that chop or modulate the clock the first 4 captured samples must be
discarded as unreliable and the skew delays accounted.
Trace Modes in Detail
All trace modes capture data from the digital inputs. Variations described in the following pages for
each trace mode apply to the analog data. The exceptions to this rule are variations that affect the
sample clock which is used for both analogue and digital data sampling.
Various delays calculated in the following sections are expressed in units of PIC Instruction Cycles
PIC which are 400 nS duration (ie 4 PIC Clocks).
TM0 - Single Channel Fast
This is the most basic trace mode and supports data capture from the primary channel only.
Upon execution of the trace T command, trace state 2 (Trigger Enabled) is immediately entered
and data capture commences without any Pre Trigger Delay (R20 is not used and can be any
value). The analogue trigger implements level sensitivity only and any values programmed to R7
Bits 4 & 5 for an edge trigger are ignored.
The post trigger delay state is entered after a valid trigger condition is seen. The duration of this
delay (T[PTD]) is calculated based upon the Time-base Expansion R13 and and Post Trigger Delay
R11 and R12 registers according to the formula:
T[PTD] = 7 + ((PTD + 1) * (5 + 3 * (TB+1))) + 2 * (PTD[hi] + 1) + U
where:
T[PTD] post trigger delay (in PIC).
PTD
16 bit post trigger delay value (R11, R12 -> 0 to 65536).
PTD[hi] 8 bit high byte of post trigger delay (R11 -> 0 to 255).
TB
8 bit time-base expansion (R13 -> 1 to 256, 0 read as 256).
U
trigger uncertainty = ± 3 PIC
The minimum post trigger delay is therefore 8 uS ± 1.2 uS and the maximum 20.342582 S ± 1.2
uS.
TM1 - Dual Channel Fast
This trace mode supports single or dual channel continuous analogue data capture and optional
enhanced edge trigger logic.
At the start of trace state 3 (ie, after the trigger), this mode implements channel alt between the
primary to the secondary channel. If both channels are programmed with the same input and
attenuation, data capture is effectively single channel. If each trace channel is programmed with a
different input (and possibly attenuation), data capture is dual channel.
The Pre Trigger Delay (trace state 1) is also implemented in this mode.
During this state and state 2 only the primary channel is captured and channel is disabled. This
ensures the trigger logic works correctly. The pre trigger delay is computed as:
T[PRE] = 10 + PRETD * (7 + 3 * (TB+1))
where:
T[PRE] pre trigger delay (in PIC cycles).
PRETD 8 pre trigger delay value (R20 -> 0 to 255).
TB
8 bit time-base expansion (R13 -> 1 to 256, 0 read as 256).
The minimum pre trigger delay is 1.2 uS and the maximum 79.3572 mS.
There is a latency of 5 to 9 PIC cycles from the trigger to the switch to the secondary channel.
The analog trigger configuration is enhanced and supports an optional edge trigger.
The post trigger delay is calculated as:
T[PTD] = 10 + 5 * N[swap] + U
N[swap] = (PTD + 1) * (TB + 2) + PTD[hi] + 1
where:
T[PTD] post trigger delay (in PIC cycles).
PTD
16 bit post trigger delay value (R11, R12 -> 0 to 65536).
PTD[hi] 8 bit high byte of post trigger delay (R11 -> 0 to 255).
TB
8 bit time-base expansion (R13 -> 1 to 256, 0 read as 256).
U
trigger uncertainty = ± 2 PIC cycles
The minimum post trigger delay is 12 uS ± 0.8 uS and the maximum 33.817092 S ± 0.8 uS and
the sample clock is stopped 3 PIC cycles after the last channel chop.
TM2 - Single Channel Expanded
This trace mode is similar to TM0: it captures data from the primary channel only.
The difference is that the capture sample period is expanded. This time-base expansion operates
by enabling data capture for one PIC cycle every P PIC cycles where P is the expanded time-base
sample period computed from the Time-base Expansion Register R13 according to:
P = 14 + 3 * (TB + 1)
where:
P expanded time-base period (in PIC cycles).
TB 8 bit time-base expansion (R13 -> 1 to 256, 0 read as 256).
The minimum time-base expansion period is 8.0 uS and the maximum 314 uS. This provides
expanded time-base sample rates ranging from 3.184 kHz to 125 kHz. At all expanded time-base
rates, 10 samples are acquired in a single burst at 25 MHz at each expanded period.
The pre trigger delay is calculated as:
T[PRE] = P * PRETD
where:
T[PRE] pre trigger delay (in PIC cycles).
PRETD 8 pre trigger delay value (R20 -> 0 to 255).
P
expanded time-base period (in PIC cycles).
The post trigger delay is calculated as:
T[PTD] = P * N + U
N = PTD + PTD[hi] + 2
where:
T[PTD] post trigger delay (in PIC cycles).
N
number of expanded capture periods.
P
expanded time-base period (in PIC cycles).
PTD
16 bit post trigger delay value (R11, R12 -> 0 to 65536).
PTD[hi] 8 bit high byte of post trigger delay (R11 -> 0 to 255).
U
trigger uncertainty = ± 2 PIC cycles
This trace mode supports the use of analog edge trigger logic.
TM3 - Dual Channel Expanded
This is a time-base expansion mode like TM2 which supports dual channel operation like TM1.
In this case data capture is enabled for 2 PIC cycles every P PIC cycles where P is computed from
the Time-base Expansion Register R13 according to:
P = 19 + 3 * (TB + 1)
where:
P expanded time-base period (in PIC cycles).
TB 8 bit time-base expansion (R13 -> 1 to 256, 0 read as 256).
The minimum time-base expansion period is 10.0 uS and the maximum 316 uS. This provides
expanded time-base sample rates ranging from 3.165 kHz to 100 kHz. At all expanded time-base
rates, 20 samples are acquired in a single burst at 25 MHz at each expanded time-base cycle.
The pre trigger delay and post trigger delay are calculated the same way as trace mode TM2
except the expanded time-base period P above is used.
TM4 - Single Channel Expanded
This trace mode is similar to TM3 except the sample clock is slowed down instead of expanded.
The slowed sample period, pre and post trigger calculations are all the same.
However unlike TM3, for each slowed sample period only one sample is acquired instead of a burst
of 20.
This mode is only available if BitScope has a variable clock rate ADC module installed (such as the
Motorola MC10319).
The Capture Engine
Bitscope uses a Microchip 16F628 PIC and a Lattice LSI 1032 PLD to implement a high speed dual
stream data capture engine. Captured data is recorded to two 32k x 8 bit SRAM buffers.
Bitscope Block Diagram
One stream is a high speed 8 bit A/D convertor.
The other records 8 inputs from the digital POD.
The captured analog and digital data is uploaded to a host computer for analysis and display.
In addition to data capture functions, Bitscope has a
frequency counter that ranges from a Hz to GHz, and an
interval and period timer that can time periods from
nanoseconds to years (if you have the time :-).
Bitscope also has sophisticated programmable triggers on
both the analog and digital inputs.
Host Interface
Communication between the host and Bitscope is via
RS-232 serial or 10BaseT ethernet.
You can think of your host computer's serial or network
port as Bitscope's communications port to which
commands are written and from which data are read.
Serial Interface

115K or 57K6 baud rate.

8 data 1 stop bit, no parity.

No hardware handshake.
Network Interface

625k baud rate.

UDP/IP Protocol.

IP Sockets API.
USB Interface

1.25 M baud rate.
Command Protocol

Single byte commands.

Atomic command execution.

Stateless protocol, easy to use.
All command bytes are simply echoed providing a handshake.
Data bytes may then be returned depending on the command.
This is what we mean by an atomic and stateless communications protocol.
Anyone who has debugged low level network problems, a computer bus, or other multi-state
system will appreciate that most problems occur in the management of state. If the protocol has no
state, and transactions are atomic, such problems don't arise in the first place.
This is why it is very easy to communicate with Bitscope
PIC Virtual Machine
The Bitscope PIC is a programmable virtual machine.

RISC style instruction set of 42 single byte instructions.

Instructions operate on a set of 46 single byte registers.

Execution is "live" via the serial port.

No programs are stored in Bitscope memory.

Programs called scripts define the operation of Bitscope.

All instruction execution is atomic which is very important.
A virtual machine design has a number of advantages.

Efficiency: each instruction may be highly optimized for performance. A general
interpreter like BASIC can do anything - but in a very inefficient way. A virtual machine
instruction is compact like assembly code, but may perform an extremely complex task.

Modularity: once a register set and basic command set are devised, extensions may be
made by adding new instructions to enhance the machine. The original instructions remain
the same.

Portability: changes to the physical machine (ie PIC) have little impact on the virtual
machine design and the software that runs on the virtual machine.
The virtual machine looks like a simple RISC CPU with a set of byte code instructions operating on
a set of byte wide registers. Virtual machine programs (scripts) are stored in the host but executed
in the virtual machine byte-by-byte as they are received on the serial port.
Because they live in host memory, scripts are not limited to the memory in Bitscope itself. The
virtual machine design means you do not need to know PIC programming to program Bitscope.
Consequently it is very easy to program Bitscope.
Programming and Usage
Using Bitscope requires three simple steps:
1.
Program registers with capture control information.
2.
Issue the data acquisition command (T, P etc).
3.
Retrieve the captured data when available (S).
At step 2, Bitscope immediately echos the command and commences acquistion, sampling analog
and digital data to its capture buffers or measuring the period, frequency or POD data. It continues
to acquire data until a programmable time delay expires following trigger assertion at which point
it terminates the capture and sends the 16 bit address of the last recorded sample to the host. After
receiving the sample address, the host may issue the sample dump command S (or M or A) to read
the captured data.
The type of data acquired and how Bitscope acquires it depends on the programming of the data
capture engine and the selected trace mode. Bitscope supports simultaneous alt/chop dual
channel analog and 8 channel logic capture, period measurement, and triggers with edge and level
condition logic as well as programmable pre and post trigger delays.
In the case where a trigger event never occurs, the host may terminate the trace by sending any
new command. In addition to this core data capture operation, the same instruction set may be
used to read and write EEPROM and program and retrieve data from any connected PODs.
Logic/Expansion POD Interface
On the front panel of Bitscope is a DB-25 logic POD connector. It provides an interface to the 8 logic
inputs. It is here you connect Bitscope's logic analyzer to the circuit under test.
In addition to the logic inputs, the POD connector
also provides access to Bitscope's analog inputs,
power and ground lines, and 2 special I/O signals,
as the schematic shows.
It is these additional signals that give Bitscope
some unique hardware expansion capabilities.
For example, it is possible to connect another
Bitscope in cascade with the first to double the
analog and/or digital inputs available without
requiring a second serial connection.
You can also connect a "Smart POD", powered by
Bitscope, to do clever things Bitscope can't do on
its own.
For some examples of Smart PODs now available check out ProtoPOD and WavePOD each of
which demonstrate some of the possibilities.
There are two methods of communicating with POD devices, be they additional Bitscopes or Smart
PODs, protocol pass-through and slow byte exchange.
Serial Interface
Bitscope's serial interface conforms to the RS-232 "standard".
Transistors Q1, Q2 level shift the serial In/Out signals.
LD1, LD2 are mounted on the back panel to monitor serial traffic between Bitscope and the host
and L2 isolates the Bitscope circuit from any high frequency noise on the serial cable.
Power Supply
Socket P1 connects to a nominal 10Vac PlugPak.
D1 and D2 form two 1/2 wave rectifiers to give us a split rail supply of ± 10Vdc.
U11 and U20 regulate +5, -5 for digital circuits.
Analog supplies +5, -5 are regulated by an isolated pair of 3 terminal regulators U9, U10.
Inductor L1 isolates the Analog ground from the Digital ground at high frequencies. In mixed signal
designs it is essential to guard against digital noise, such as like ground bounce, getting into the
analog circuits.
1 GHz Prescaler
The 1GHz prescaler chip takes a high frequency signal and outputs a f/64 square wave.
By including a switch (S3) and a 50 ohm resistor it is possible to switch in a prescaler device to
drive SCLK/Y2 (pin 33) on Spock.
Spock can then be set to route this through to the PIC via Event 1 in Trigger Source R7 for
counting, giving us a means of measuring frequencies up to 1 GHz.
S3 switches in the prescaler with a 50 ohm terminator to BNC CH-B. This has other benefits. It
means that we can use Channel B as a 50 ohm terminated input.
For example, channel B with S3 on could be used as a Ethernet cable terminator with the ability to
sample the network traffic for display on a PC.
Expansion POD Interface Circuit
The expansion POD interface
uses a transparent buffer U12
which latches the 8 logic levels
for writing into the SRAM buffer
via the digital data bus.
This buffer has an optional input
pulldown resistor network RN1 which is nominally 100K.
The pulldowns ensure that if nothing is connected to a POD input it floats to ground.
It also means the input impedance is 100K.
If your application requires a higher input impedance, RN1 may be omitted without detriment to
the design. Analog switch U22 connects RNG0 and RNG1 signals from the PIC to the Logic POD.
These signals are active during SHIFT mode and enable serial communications with a "Smart
POD" via the IO-0 and IO-1 pins on the Logic POD connector.
Vraw+, Vraw- are available through 500 mA poly fuses at the POD connector. This allows external
POD devices to be powered from the Bitscope itself. +5 regulated is also available.
Also 2 analog signals are brought in via the Logic POD. These are the 3 rd and 4 th analog channels
(selected via PG0 option in Spock). These signals have analog grounds which should not be
connected to digital grounds.
Logic POD Ideas
The following ideas suggest uses for the Logic/Expansion POD connector.
The minimum "POD" is just a 25 way ribbon cable terminated by a pin header for connecting probes
to the circuit under test.
A more sophisticated example is our own Proto POD.
The I/O control signals make it possible to have "smart POD" devices that can provide extra
functionality.

Logic Analyzer POD with active TTL level Buffers with signal conditioning.
Logic Lab POD - a breadboard POD including supplies and Digital/Analog monitoring for
circuit development. I/O pins used for configuration.
Serial protocol analyzer - serial stream fed through a shift register which is monitored by
Spock TRIG function to detect sequential patterns.

10 Bit Logic Analyzer - 8 level + 2 Analog logic

Differential voltage probe for analog signals

High voltage, or millivolt active probes for analog channels.

Data Acquisition POD - Current, Voltage, Temperature etc resolved and stored as bytes to
Logic RAM, handshake via I/O pins

PIC Programmer POD

Spectrum Analyzer POD
Video Capture POD - capture 8 full video lines for analysis,

Component Tester

SONAR POD
High Speed ADC Module
Our new technology ADC module for Bitscope
plugs into the existing PCB to extend analogue
data capture bandwidth beyond 70 MHz.
Check out these features:

3dB input bandwidth beyond 70 MHz.

Sample rate up to 40 MHz.

Subsample data aquisition to 100 MHz.

Low noise surface mount design.

Diode circuit clamps input voltage.

Plug-in replacement for existing ADC.
It is available now from our online store.
Unlike the Motorola MC10319 or Exar 8786 it replaces, this ADC can be used with Bitscope's clock
doubler circuit. However, whether you want to do this will depend on your data capture application.
Further, using sub-sampling techniques, is it possible to capture signals up to 100 MHz even when
running it at a sample rate of 25 MHz. These and other interesting subjects are discussed in the
following pages.
ADC Development History
BitScope was originally designed to use the now discontinued Motorola MC10319 25MS/S ADC. The
MC10319 is a bipolar chip design which combines wide bandwidth with completely static operation.
It was a good choice for BitScope as it came in a 24 pin DIP package allowing future replacement
by a PCB module. Its static bipolar design allowed simple software loops to control the timebase,
and the direct conversion via a comparator tree meant no pipeline delay when sampling data.
Older ECL and bipolar chips like the MC10319 are no longer viable and most manufacturers have
now discontinued them. They draw excessive power, and require old and expensive fabrication
processes that are no longer used.
These days, most chips are CMOS which
means they are cheap and fast. The most
popular ADC after the Motorola device was the
EXAR 8786 which is rated to 30MS/S.
We offer this chip in a low cost replacement
ADC module (pictured left) for use with
Bitscope.
It is a good alternative to the MC10319 but
while it can operate at a slightly higher sample
rate it has a more limited input bandwidth.
More recently, a number of new technology ADC chips that promise much higher bandwidth and
capture precision have been released by Texas Instruments, Analog Devices, National
Semiconductor and others.
After extensive evaluation and testing, we have found the TI5540 ADC to be the best example of
this new converter technology for use in Bitscope, and our surface mount ADC module is based on
this chip. It has excellent noise immunity and is fast enough to make full use of Bitscope's 100 MHz
analogue input bandwidth circuitry. Also, the TI5540's 2V input span matches the MC10319
maintaining exactly the same voltage ranges with both chips.
ADC Module Specification
The new ADC module uses the TLC5540 high-speed, 8-bit "analog to digital" converter (ADC) that
converts at sampling rates up to 40 megasamples per second (MSPS).

8-Bit resolution.

Differential Linearity Error.
±0.3 LSB Typ, ±1 LSB Max (25°C)

Integral Linearity Error.
±0.6 LSB Typ, ±0.75 LSB Max (25°C)

Sample rate of up to 40 MHz.

Internal sample-and-hold function.

5-V single supply operation.

Low power consumption (~85 mW Typ)

Analog Input Bandwidth (>75 MHz Typ)

Internal reference voltage generators
This ADC is a CMOS "semiflash" converter which uses pipelined dynamic conversion to achieve its
high performance. The functional diagram below shows the pipeline architecture which results in a
4 sample delay between analogue data capture and digital data conversion.
Because the sample is held as a charge, conversion accurracy depends on the sampling rate. That
is, this chip prefers a fast clock, but not too fast as the 40 MHz option explains. The design also
allows a much shorter aperture time which translates to a higher input capture bandwidth; very
useful when sub-sampling.
This compares with the original MC10319 ADC, which being a single stage bipolar "flash" converter
means minimal propagation delay, but which is not capable of achieving such high input bandwidth
data capture.
Bandwidth vs Sample Rate
The subject of DSO "bandwidth vs sample rate" is one that seems to cause much confusion.
To those familiar with the sampling theorem, it seems strange that an ADC that has a maximum
sample rate of 40 MHz is able to measure signals up to 75 MHz, let alone being able to even see
anything at 100 MHz or more.
However, under the right circumstances it is quite possible to do all this and more...
Periodic waveforms
The key to understanding how this "magic" works is to realize that most signals of interest to an
oscilloscope user are invariant periodic. That is, they a have fixed frequency and wave shape.
Indeed it is not easy to see any other type of signal with an analogue CRO.
A DSO like Bitscope can of course capture and display a non-periodic waveform, but if we're
interested in seeing signals with frequency content higher than half the sample rate, as the
specification of this new ADC suggests we can, then it too will be limited to periodic waveforms.
ADCs used in DSOs like Bitscope are designed to exploit this contraint by sampling the analogue
input for a much shorter time span than a sample period. That is, they have a short "aperture" (ie,
time to capture the input signal) but a require longer time to convert the analogue sample to its
binary output value (ie, one sample period).
The short aperture allows the ADC to "see" a maximum frequency much higher than the sample
rate alone might suggest, but there is some work to do first to make sense of the data.
Sub-sampling waveform capture
If you display a buffer of raw data captured from a signal with higher frequency than half the
sample rate, you will still see a waveform; just not the right one ! Instead you will see an "alias",
or frequency shifted version of the waveform. However, if certain conditions are met, the alias is
unique, meaning you can "unwrap" the raw data to reveal the true waveform.
This process is known as sub-sampling and is a technique used by most modern DSOs to capture
very high frequency signals. It is similar to a radio circuit where two frequencies are "mixed" to
produce the "sum and difference" to shift from high frequency to a lower one. Indeed, ADCs like
this one are often used to perform this very function in systems like cellular telephones.
So, when you read a specification that says "DSO X has a 100 MHz bandwidth but a 20 MHz sample
rate" you'll know it means that using sub-sampling, the DSO can display a periodic waveform with
frequency components up to 100 MHz.
Using this ADC, you can say "Bitscope has a bandwidth of 75 MHz and a sample rate of 40 MHz.
An extreme sub-sampling example
It must be remembered that the analogue circuitry must have an input bandwidth sufficient to pass
the signal to the ADC without distortion. Bitscope's analogue inputs have a 3dB bandwidth of 100
MHz. It is even possible to "see" signals at higher frequencies if you are not concerned that the
signal will be somewhat attenuated. For example, the following screen-shot shows a 125 MHz
signal captured using the new ADC module.
ADC 5540 converter captures a 125MHz sine wave.
This signal was captured running the ADC at 25 MHz using sub-sampling to unwrap the display.
Circuit Design
The ADC5540 module is designed to function similarly to the original MC10319 chip.
Schematic Diagram
You will notice from the schematic that there are a couple of extra components to set the VIN span
and clip overvoltage inputs.

R1 and R2 generate Vm and allow trimming of Input SPAN to exactly 2.0V. Vm is used to
calibrate the ADC range to the middle of the input voltage.

D2 diode clamps the input signal from going negative.

D1 moves the ADC range up from GND (0.4V) to improve linearity for signals near 00h.

R3 dampens the CLK signal to impove performance at high frequencies.

C1-C6 decouple supplies to ground minimising noise.
ADC 5540 module schematic (click here for PDF version).
PCB Layout
Key to the performance of this high speed converter is the PCB design...
We have employed low noise
surface mount technology with all
the SMD components placed on
the underside of the PCB.
This helps shield the sensitive
circuit from noise by placing the
active components "upside down"
so they are located between the
ADC module's ground plane and
the BitScope PCB.
Note the location of the ground
plane which is as large as practical
ADC 5540 module layout (enlarged x 2.5)
and arranged to shield critical
signals.
Signal Clipping
Sometimes the signal applied to BitScope may cause a signal in excess of 2Vpp at the ADC.
The input chain has been designed to ensure that the
ADC will clip the signal. The positive clipping is handled
by the ADC since the OP AMP driver runs from +/-5V,
Vin at the ADC must always be less than +5. For
negative clipping a schottky diode is used on the
ADC5540 module so Vin never exceeds -0.4V, which is
within spec for the ADC chip.
Clipping shows limit of ADC span
With previous ADC modules Bitscope included a pair of back to back diodes for signal clipping.
These diodes are not required with the ADC5540 module.
40 Mhz option
The new ADC module gives you the option of sampling data at 40 MHz.
Bitscope is normally configured to drive the ADC at 25 MHz and must be modified to run at 40 MHz.
However, before you leap in and do this, you may wish to consider some of the trade-offs.
Aperiodic Waveform Capture
If the signals you are interested in are periodic, then sub-sampling allows you to measure
frequencies beyond 70 MHz running the ADC at only 25 MHz. Indeed, for reasons described below
it is preferable to run the ADC at this lower rate.
However, if you wish to capture aperiodic waveforms or one-shot events, and the frequency
content of these signals is greater than 12 MHz (ie, half the 25 MHz sample rate), then running the
ADC at 40 MHz will allow you to see frequency components up to 20 MHz.
Converter performance
The ADC5540 converter performance varies with sample clock frequency. A close look at the data
sheet shows that the ADC begins to lose ENB (effective number bits) when clocked at its maximum
rate. This shows up as nonlinearity (noise) imposed on the signal which increases with input
frequency.
Some real-world examples demonstrate the difference...
This trace shows the ADC is capable of
sampling a 100MHz sinewave using the
sub-sampling technique discussed earlier.
There is some noise evident and the signal is
attenuated due to the very high frequency of
the input signal.
ADC @ 25 MHz - 100 MHz Sinewave ~300mVpp
Another sinewave, now sampled at 40 MHz,
exhibits more noise. This is due to the lower
ENB and slightly increased jitter resulting from
the clock doubler circuit. Large signal
performance is not affected, however so you
will need to consider which is more important
to you.
ADC @ 40 MHz - 70 MHz Sinewave ~300mVpp
Memory Usage
Another issue is sample memory usage. A 40 MS/s Bitscope will consume sample RAM twice as fast
and limit the maximum capture to about half. Alternatively, if you normally capture less than a full
buffer of data, running at 40 MS/s means you will generate up to 2 times as much data which will
slow the serial link upload time.
Logic Analysis
If you plan to use Bitscope as a high speed logic analyzer with simultaneous analogue signal
capture, you may want to run the clock at 40 MHz. This will allow you to capture logic transitions
at almost twice the speed of the standard Bitscope.
Modifying Bitscope for 40 MS/s
Bitscope is capable of being clocked at up to 50MS/s limited by the PLD, SRAM, and the PIC
microcontroller. The 40 MS/s limit described here is due to the ADC module, and the standard 80
MHz PLD and 15 ns SRAM components. If you are not interested in analogue data capture (ie,
you're not using an ADC), you can in fact clock Bitscope at 50 MS/s for use as a very high speed
logic analyzer if you use a 100 MHz PLD, 12 ns SRAM and omit the ADC.
To run Bitscope at 40 MS/s you have two choices; either install an 80 MHz OSC module to replace
the standard 50 MHz part, or enable the clock doubler circuit and use a 40 MHz OSC module.
The following notes detail a board level modification to Bitscope which should only be attempted by
an experienced person. Desoldering components from a multilayer card must be done carefully
with appropriate tools to avoid damaging the PCB.
1.
2.
Install and test ADC5540 module at 25MHz.
o
Insert ADC5540 module in 24 pin socket, observing Pin 1
o
Make sure 3 pin header (above ADC) is 1-2 OPEN, 2-3 SHORTED
o
Set SPAN (RV2) so TP3-TP4 is 1.0V
o
Set ADC midpoint (RV1) so TP5-TP4 is 0.0V
o
Remove D5, D6 to use ADC5540 clipping circuits. (cut the leads at one end is OK)
If not using the clock doubler circuit (default).
3.
o
Remove U19 50MHz OSC module
o
Install 80MHz OSC module in U19
If using the clock doubler circuit (advanced).
o
Remove U19 50MHz OSC module
o
Install 40MHz OSC Module in U19 - test this configuration (20MS/s capture rate)
o
Remove shorting link at C54 (20pF)
o
Install C54 - 22pF
o
Install R11 220R nominal, 150R - 330R possible range (optionally adjust for best
results at 40MS/s)
Notes
1.
The new ADC has pin 1 clearly marked - make sure it is inserted correctly!
2.
If you upgrade to 40MHz using the 80MHz OSC module, it is not easy to go back. Only do
this mod if you are confident in your technical abilities.
3.
If you use the 40MHz clock doubler circuit, you can revert to a non-doubled clock by
shorting C54. This will allow you to operate at 40MS/s or 20MS/s without too much
trouble.
4.
The clock doubler relies on C54 and R11 to act as a delay line for the second XOR gate
input. The gate characteristics of the AC86 device you use may affect this operation
slightly. To get the best x2 clock from the XOR gate may require altering R11 a little either
way. This may reduce clock jitter and give better ADC performance at 40MS/s.
How the clock doubler works
Normally, Bitscope uses a x2 Oscillator module with a synchronizing flip-flop to generate zz-clk
(the sample clock). To allow more commonly available OSC modules to be used at sample rates of
40MHz (80MHz OSC), a simple clock doubler circuit is included in the Bitscope design. This circuit
is normally disabled, but can be activated by adding an RC filter.
Bitscope clock circuit
Refering to the schematic above:

With C54 shorted and R11 omitted, U3D simply buffers the OSC module.

With C54 and R11 in place, the signal at U3D/12 is a delayed version of the signal at
U3D/13

U8A generates a synch clk (zz-clk) which is half the freq of the signal at pin 3
The XOR timing diagram below shows how a x2 clock is generated.
ADC Comparisions
The following images show you some screen dumps from Bitscope capturing real waveform data
showing how various ADC modules behave under similar circumstances.
ADC5540 @ 25 MHz
This trace shows good linearity and low noise.
800 kHz Sinewave ~1Vpp
ADC shows typical tendency to flip between
adjacent states. This looks like noise, but it is
the resolution of the 8 bit converter.
Least sensitive range, no signal
High gain range (+/-130mV). From the
previous trace of the 3V range, it can be seen
that noise at the ADC itself is less than 1 bit.
This trace therefore shows the noise floor in the
Bitscope input stage - about 3mVpp - which
is just over 1% FS.
Most sensitive range, no signal
ADC5540 @ 40 MHz
800 kHz Sinewave ~1Vpp
Least sensitive range, no signal
Module performance is slightly degraded by
clocking it at the 40MHz rate. This is a
characteristic of these semi-flash converters their performance is a function of clock rate
and input frequency.
Most sensitive range, no signal
EXAR8786 @ 25 MHz
This trace shows that the EXAR converter
begins to lose ENB at 25MS/S
800 kHz Sinewave ~1Vpp
Low level noise in EXAR converter is scaled
according to range. About 2% FS shows up as
100mV noise on this range. In any 8 bit DSO,
this scaled noise needs to be allowed for.
±3V range, no signal
Exar converter exhibits about double the noise
figure of the new ADC5540 ADC - 6mVpp or
2.3% FS. On this range a small component of
the noise is due to the DIP PCB module which
can not be shielded as well as the new SMT
assembly.
Most sensitive range, no signal
MC10319 @ 25 MHz
800 kHz Sinewave ~1Vpp
±1V range, no signal
The Motorola chip is subject to more noise than
the TI5540. Some of this is the digital
switching noise caused by the bipolar
technology and higher currents operating in
the chip.
Most sensitive range, no signal
BILL OF MATERIALS (BK300S)
Category Description
Part
Footprint Qty Designators
Capacitor ELECTROLYTIC 1000uF 25V
1000uF
5mm PCB
Capacitor ELECTROLYTIC 2200uF 25V LOW ESR
2200uF
7.5mm
PCB
1
C3
1
C10
C44, C45,
Capacitor TANTALUM 25V 1uF
1uF
5mm
6
C61, C62,
C65, C66
Capacitor TANTALUM 25V 10uF
10uF
5mm
2
C39, C42
Capacitor MKT 63V 100nF
100nF
5mm
2
C34, C32
Capacitor CERAMIC 50V 6pF
6pF
5mm
1
C78
Capacitor CERAMIC 50V 8pF
8pF
5mm
2
C31, C33
1
Capacitor CERAMIC 50V 8pF
8pF
5mm
2
C72, C73
1
Capacitor CERAMIC 50V 100pF
100pF
5mm
1
C27
Capacitor CERAMIC 50V 220pF
220pF
5mm
2
C13, C19
Capacitor CERAMIC 50V 10nF
103
5mm
1
C50
C4,
C5,
C6,
C7,
C8,
C9,
C11, C12,
C14, C17,
C18, C21,
Capacitor MONO BYPASS 100nF 50V
104
5mm
43 C22, C23,
C24, C25,
C26, C28,
C29, C30,
C35, C36,
C37, C38,
C40, C41,
Category Description
Part
Footprint Qty Designators
C43, C46,
C47, C48,
C49, C51,
C52, C53,
C55
C63,
C64, C67,
C68, C70,
C71, C76,
C77
TRM3,
Capacitor TRIM CAP miniature WHITE
10pF
5mm
2
Capacitor TRIM CAP miniature GREEN
30pF
5mm
2
Resistor
RESISTOR M/F .25W 1%
18R
R500
1
R69
Resistor
RESISTOR M/F .25W 1%
22R
R500
1
R50
Resistor
RESISTOR M/F .25W 1%
51R
R500
2
R21, R38
Resistor
RESISTOR M/F .25W 1%
100R
R500
3
Resistor
RESISTOR M/F .25W 1%
120R
R500
1
Resistor
RESISTOR M/F .25W 1%
220R
R500
4
Resistor
RESISTOR M/F .25W 1%
270R
R500
1
R68
Resistor
RESISTOR M/F .25W 1%
330R
R500
1
R39
Resistor
RESISTOR M/F .25W 1%
330R
R400
1
R75
Resistor
RESISTOR M/F .25W 1%
360R
R500
1
R32
Resistor
RESISTOR M/F .25W 1%
430R
R500
1
R37
Resistor
RESISTOR M/F .25W 1%
470R
R500
2
R42, R43
Resistor
RESISTOR M/F .25W 1%
1K0
R500
8
1
TRM4
TRM1,
1
TRM2,
R54, R29,
R33
R35
R30, R31,
R40, R67
R3,
R7,
R8,
R9,
R41, R57,
R58, R62
Resistor
RESISTOR M/F .25W 1%
2K2
R500
2
R4, R12
Resistor
RESISTOR M/F .25W 1%
15K
R500
1
R60
Resistor
RESISTOR M/F .25W 1%
3K9
R500
1
R1
Resistor
RESISTOR M/F .25W 1%
4K7
R500
7
R2,
R18,
R55, R61,
1
Category Description
Part
Footprint Qty Designators
R65, R70,
R72
Resistor
RESISTOR M/F .25W 1%
5K6
R500
1
R53
1
R5, R6, R10,
Resistor
RESISTOR M/F .25W 1%
10K
R500
8
R56,
R59,
R63,
R64,
R71
Resistor
RESISTOR M/F .25W 1%
22K
R500
1
Resistor
RESISTOR M/F .25W 1%
51K
R500
4
Resistor
RESISTOR M/F .25W 1%
510K
R500
4
IC
14 DIP analog Switch
HCF4066
14 DIP
1
U22
IC
20 DIP Buffer
74HC245
20 DIP
2
U4, U5
IC
20DIP Latch
74HC573
20 DIP
1
U12
IC
28 DIP SRAM
CY7C199-15
28 DIP
2
U6, U7
IC
8 DIP COMPARATOR/ (Optional Module)
TL714C
8 DIP
1
U26
IC
DIP 14 DAC
TLC5620
14 DIP
1
U21
IC
DIP 16 DAC
TLC7524
16 DIP
1
U19
IC
DUAL OP-AMP
TL 072
8 DIP
1
U27
IC
DIP 16 MUX 74HC4052
MUX-4052
16 MUX
2
U17, U18
IC
AD8047
OP-71
8 DIP
2
U14, U16
IC
MAX477
OP-71
8 DIP
1
U15
OP-71
8 DIP
2
U23, U24
TL072
8 DIP
1
U28
OP-72
8 DIP
1
U25
2
IC
IC
IC
TLC071 (Socket for optional 100MHz
upgrade)
DUAL OP-AMP
TLC072 (Socket for optional 100MHz
upgrade)
R66
R19, R20,
R22, R23
R25, R26,
R27, R28
1
1
2
IC
TO-220 REG
LM2575-05
TO-220
1
U8
4
IC
TO-220 REG
7805
TO-220
2
U9, U11
4
IC
TO92
78L08
TO92
1
U29
IC
TO-220 REG
7905
TO-220
1
U10
IC
TO92
79L05
TO92
1
U20
IC
MACH SOCKET 24 PIN PCB
SYNCHRO
24 DIP
1
U3
4
Category Description
Part
IC
MODULE 24 PIN PCB
ADC-5540
Semi
LED 3MM YELLOW
Semi
Footprint Qty Designators
24 DIP
1
YELLOW
2.54mm
4
LED 3MM RED
RED
2.54mm
1
LD2
3
Semi
LED 3MM GREEN
GREEN
2.54mm
1
LD1
3
Semi
1A RECT
1N4002
10mm
1
D1
Semi
SIGNAL
1N4148
10mm
6
U13
LD3, LD4,
LD5, LD6
D5,
D7,
D8,
D9,
3
D10, D11
Semi
Semi
HI SPEED DIODE
TO-92 NPN
1N5819
BC548
10mm
TO92
1
5
D2
Q2,
Q4,
Q6,
Q7,
Q8
Q1,
Semi
TO-92 PNP
BC558
TO92
3
Misc
TOROID
100uH
PCB VERT
1
L2
Misc
WIRE LINK
LINK
1
L1
Misc
T60 030 Polyfuse
200
Misc
SOCKET PLCC-44
PLCC-44
Misc
RA PCB SPDT Long
Misc
Q3,
Q5
FUSE1,
5mm
2
PLCC44
2
U1, U2
SPDT
2
S1, S2
RA PCB SPDT Short
SPDT
1
S3
Misc
2.5mm DC Socket
SOCKET
1
P1
Misc
RA 25 F D Type
DB25-F
1
P4
Misc
RA 25 M D Type
DB25-M
1
P5
Misc
RA PCB connector
BNC
2
CN1, CN2
Misc
LINK 1-2 (20MHz option)
CPU-CLK
Notes
1
OVERLAY INCORRECT
SAMPLE is CORRECT
2
MODULE SHOWS U location
3
BEND LEDs as SAMPLE
6mm BODY to BEND
FUSE2
JP1
1
1
Category Description
Part
4
M3 bolt as per SAMPLE
5
15mm SPACERS - SAMPLE
6
HOLE under U11 - NO SOLDER
Footprint Qty Designators
BILL OF MATERIALS (BK220S)
Category Description
Part
Footprint Quantity Designators
Capacitor 1000uF 25V Electro
Generic
ELEC200
2
C15 C3
Capacitor 470uF 25V Electro
Generic
ELEC200
2
C4 C16
Capacitor 100uF 25V Electro
Generic
ELEC100
2
C19 C20
Generic
TANT200
2
C42 C39
Generic
TANT200
6
Generic
CAP200
2
C32 C34
Generic
CER200
1
C13
Generic
CER200
2
C27 C53
Capacitor 1nF 50V Ceramic 5mm Generic
CER200
2
C59 C60
Generic
CER200
3
C31 C33 C58
Generic
CER200
2
C1 C2
Capacitor 20pF Ceramic
Generic
CER200
1
C54
Capacitor Cspeed option
Generic
CER200
1
C69
Capacitor Cspeed option
Generic
CER200
1
C57
Capacitor Cspeed option
Generic
CER200
1
C56
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
10uF
16V
Tantalum
5mm
1uF
16V
Tantalum
5mm
100nF 63V MKT Poly
5mm
100nF
50V
Ceramic
5mm
10nF
50V
Ceramic
5mm
100pF
50V
Ceramic
5mm
20pF
50V
Ceramic
5mm
C44 C45 C61 C62
C65 C66
C70 C71 C68 C67
C64 C63 C30 C51
C50 C49 C48 C47
Capacitor
100nF Mono Bypass
5mm
C46 C41 C38 C37
Generic
CAP200
41
C10 C7 C24 C23
C52 C43 C40 C22
C21 C14 C17 C18
C25 C28 C29 C35
C36 C55 C5 C6 C8
Category Description
Part
Footprint Quantity Designators
C9 C11 C12 C26
Diode
1N4002 100V 1 Amp
Generic
D400
2
D12 D13
Diode
1N4002 100V 1Amp
Generic
D400
2
D2 D1
Diode
1N4148
Generic
D300
9
DIP28N
2
U6 U7
IC
5C2568 32Kx8 SRAM Cypress
20/15nS
CY7C199-15
D3 D4 D5 D6 D7
D8 D9 D10 D11
IC
74AHC74 Dual D Type TI
DIP14
1
U8
IC
74AHC86 Quad XOR
TI
DIP14
1
U3
Generic
DIP20
1
U12
IC
74HC573 Transparent
Latch
IC
7805 +5V 1 Amp
Generic
TO-220H
2
U9 U11
IC
7905 -5V 1Amp
Generic
TO-220H
2
U10 U20
IC
AD8048 AV=5 OP AMP Analog Devices
DIP8
1
U15
Generic
DIP14
1
U22
Maxim/Generic
DIP16
2
U4 U5
Maxim/Generic
DIP16
2
U17 U18
DIP8
4
U14 U16 U23 U24
DIP24
1
U13
DIP8
1
U25
1
U19
IC
IC
IC
IC
IC
IC
IC
IC
74HC4066
QUAD
Analog Sw
MAX4051/74HC4051
AN SW
MAX4052/74HC4052
AN SW
MAX477/AD8047
Maxim/Analog
300MHz OP AMP
Devices
MC10319 ADC Module Motorola
MC12073 / SAB6456A
Prescaler
DIP-OSC 50/40 MHz
PIC
16F84-10
Motorola/Philips
Generic
DIP14
/
DIP8
MicroChip
Socket
1
U1
Lattice
Socket
1
U2
Generic
TO-92
4
Q6 Q7 Q8 Q9
Transistor BC548 NPN Signal
Generic
TO-92V1
3
Q2 Q3 Q10
Transistor BC558 PNP Signal
Generic
TO-92V1
3
Q1 Q5 Q12
LED
Generic
LED-3mm
1
LD2
IC
JFET
(PROGRAMMED)
LATTICE
ispLSI
1016-80 (PROG)
J309/J310 JFET
RED 3mm LED
Category Description
Part
Footprint Quantity Designators
LED
GRN 3mm LED
Generic
LED-3mm
1
LD1
LED
YEL 3mm LED
Generic
LED-3mm
4
LD3 LD4 LD5 LD6
Resistor
10K
R400
5
R27 R10 R5 R6
Resistor
110R
R400
1
R33
Resistor
120R
R400
1
R35
Resistor
150R
R400
1
R24
Resistor
18K0
R400
2
R19 R22
Resistor
1K0
R400
5
R36 R9 R8 R2 R41
Resistor
1M0
R400
2
R28 R26
Resistor
220R
R400
5
Resistor
2K2
R400
2
R4 R12
Resistor
330R
R400
1
R39
Resistor
430R
R400
1
R37
Resistor
470R
R400
1
R11
Resistor
470R
R400
2
R1 R32
Resistor
47K
R400
2
R42 R43
Resistor
4K7
R400
5
Resistor
50R
R400
1
R21
Resistor
5K6
R400
1
R34
.25W
Metal
Film
Metal
Film
Metal
Film
Metal
Film
Metal
Film
Metal
Film
Metal
Film
Metal
Film
1%
.25W
1%
.25W
1%
.25W
1%
.25W
1%
.25W
1%
.25W
1%
.25W
1%
.25W
Metal
Film
Metal
Film
Metal
Film
Metal
Film
Metal
Film
Metal
Film
Metal
Film
1%
.25W
1%
.25W
1%
.25W
1%
.25W
1%
.25W
1%
.25W
1%
.25W
Metal
Film
Metal
Film
1%
.25W
1%
R29 R30 R31 R38
R40
R3 R7 R18 R20
R23
Category Description
RES-NET
9R
1Common
100K
R-NET
Part
Footprint Quantity Designators
84RGSD9X310
SIP10
1
RN1
TrimPot
200R
Generic
TRIM-V
2
RV3 RV4
TrimPot
330R
Generic
TRIM-H
1
RV2
TrimPot
4K7
Generic
TRIM-H
1
RV1
2
FUSE1 FUSE2
PolyFuse
500mA
Resettable
Poly Fuse
RAYCHEM RXE-050 C200
Inductor
150uH Axial RF Choke Generic
L500
2
L1 L2
Crystal
4 10 20 MHz
Generic
HC18/U
1
Y1
IC Socket 18 Pin Socket
Generic
DIP18
1
U1
IC Socket 44 Pin PLCC Socket
Generic
PLCC44
1
U2
BNC-H
2
J1 J2
Hardware
BNC RA PCB 50ohm OUPIIN
Low Profile
08928-B1/50
OUPIIN
Hardware DB25-Female
DB25RA/F 1
P4
DB25RA/M 1
P5
DC-PLUG
1
P1
SPDT-RA
3
S1 S2 S3
M3
5
M1 M2 M3 M4 M5
Hardware Insulating Silicone Pad
TO-220
4
Hardware Mounting Bush
TO-220
4
M3
4
M3
5
07906-25FA
OUPIIN
Hardware DB25-Male
Hardware
SOCKET
07906-25MA
RA
PCB
2.5mm
Hardware SPDT T RA PCB Toggle
Hardware
Hardware
Spacer M3 15mm Hex
Threaded
Mounting
screw
nut
washer M3
Hardware Mounting Screw
Hardware PCB BitScope-11
Extruded
Metalwork
Case
Aluminum 3mm wall
W = 150mm H=50mm
Front Panel 1.2mm AL
Lexan
Salcom
TS40T-TS-8-TE1CR
1
L=160m
Metalwork
Generic
PCB1
Category Description
Metalwork
Part
Footprint Quantity Designators
Rear Panel 1.2mm AL
Lexan
BitScope 220 Panels
BITSCOPE NETWORKING
Browse this part of the website to learn about:
1.
Bitscope Networking and what it means.
2.
How networking works and the benefits it provides.
3.
Network interface hardware design with schematic.
4.
The network protocols and packet formats used.
5.
Network interface configuration and programming details.
6.
Free networking toolkits and software you can download.
BitScope networking was first implemented in BS220 and BS300 via an external adaptor; an
RS-232 serial to 10BaseT ethernet convertor custom designed for use with these Bitscopes.
Network Adaptor Module
This allowed a single or multiple PCs to be used with as many Bitscopes as required,
simultaneously.
In addition to converting between ethernet and serial formats the adaptor knew how Bitscope's
VM-220 and VM-300 modules and Serial Interface work together to provide a dramatic
increase upload speed while maintaining efficient network utilization.
Since then BitScope's networking technology has been integrated into the current model Network
BitScopes for seamless network operation opening up a whole range of remote testing,
automated diagnostics and other networked data acquisition applications.
Networking Advantages

Multiple Network Bitscopes may be connected simultaneously to a single PC.

The data upload speed is increased from 115 kb/s to 1.25 Mb/s per Bitscope. In
particular this makes possible high rate refresh DSO style applications.

Removes the distance limitations associated with RS-232. The PC and its Network
Bitscope(s) can be geographically remote: from the next room to around the world.

A single software application may simultaneously control many (eg, hundreds) of Network
Bitscopes. This capability enables the virtualization of larger Bitscopes.

Open Standard Internet Protocols (UDP/IP) are used for all communication. This allows
the development of new generation of Bitscope applications such as remote monitoring,
remote control, Bitscope sharing, distance learning etc.

Use of the standard IP stack and "sockets" interface eliminates custom serial handlers and
makes possible the development of applications that can readily be deployed across
different hardware and software platforms.

Backward compatible with all BS300 series Bitscopes (after installation of the upgrade).

The adaptor version is self contained and powered by the Bitscope itself.

Ethernet isolation means BitScope is also electrically isolated from the PC.
NETWORK HARDWARE
All Network BitScopes employ the same innovative technology first pioneered in the original
Bitscope Network Adaptor; a self contained add-on module powered by the Bitscope to which it is
connected.
The adaptor was housed in a DB25 to RJ45 connector shell that a that plugged directly into a BS200
or BS300 series Bitscope serial interface.
The hardware comprised a PIC 16F876 and RealTek RTL8019AS 10BaseT ethernet chip with
associated circuitry all mounted on a small surface mount PCB designed to clip into the shell.
Network Adaptor Module
The PIC implemented most of the functionality of the adaptor including the UDP/IP protocol stack,
data handling and buffering, high speed serial interface with Bitscope and RealTek ethernet chip
control.
The RealTek chip and YCL FTC1111-01 filtered RJ45 socket form the 10BaseT ethernet interface.
The network adaptor was designed to work with the BS220 series VM-220 and VM-300 VM chips
enabling support for burst communications speeds of up to 1.25Mb/s and queued commands (for
efficient operation over ethernet).
The schematic below shows the adaptor circuit diagram (click on it to see a larger image).
All current model Network BitScope's are built using similar designs except that now the network
interface is integrated into the BitScope itself and no intermediate serial interface is required.
NETWORK PROTOCOL
Bitscope Networking uses the User Datagram Protocol (UDP) for PC/Bitscope communication.
UDP is one of two transport protocols used by the Internet (the other being TCP).
UDP is encapsulated in Internet Protocol (IP) datagrams which means communications between
the PC and a Network Bitscope can be routed across multiple networks or even the Internet itself.
Below is the format of the UDP/IP packet implemented by the Network Adaptor.
4
8
16
32 bits (IP Header)
Ver.
IHL
Type of Service
Total Length
Identification
Time To Live
Flags
Protocol
Fragment Offset
Header Checksum
Source Address
Destination Address
Option plus Padding
16
32 bits (UDP Header)
Source Port
Destination Port
Length
Checksum
32 bits (UDP Payload)
Bitscope Packet
CRC
UDP/IP Packet Format
Most of this is transparent to the user and/or programmer of a Network Bitscope.
The only part that is of interest to Bitscope programmers is the Bitscope Packet.
QUEUED COMMANDS
The VM-220 and later chips support a maximum burst data rate of 1.25 Mb/s.
This is made possible by a new hardware UART and queued commands handling in VM-220 and
VM-300 chips and network integration in the newer BitScope models.
The original Bitscope adopted a simple atomic and stateless Command Protocol where each
command was echoed in acknowledgement. The host PC simply waited for the reply of the previous
command to know when to proceed with the next one.
This was well suited to serial communications, made programming Bitscope easy and data
transfers reliable. However, tight hand-shake protocols such as this are not desirable when the
communication takes place over packetized and fixed overhead transport mediums like Ethernet or
USB.
Bitscope command op-codes fall into two categories: simple commands for which a single reply
byte (the command itself) is returned, and complex commands where the reply byte is followed by
one or more data bytes (depending on the command).
The Network Adaptor allows multiple (simple) commands (and optionally one complex command)
to be grouped together and sent in a single Command Packet between the PC and the adaptor.
The adaptor feeds the commands to Bitscope, checking the reply byte returned for each one,
before sending a Reply Packet with all the acknowledgement bytes back to the PC.
If the last command in the group is a complex command, the data produced by the command is
appended to the reply. If more data than one packet is produced, multiple packets are returned.
QUEUED COMMANDS
The VM-220 and later chips support a maximum burst data rate of 1.25 Mb/s.
This is made possible by a new hardware UART and queued commands handling in VM-220 and
VM-300 chips and network integration in the newer BitScope models.
The original Bitscope adopted a simple atomic and stateless Command Protocol where each
command was echoed in acknowledgement. The host PC simply waited for the reply of the previous
command to know when to proceed with the next one.
This was well suited to serial communications, made programming Bitscope easy and data
transfers reliable. However, tight hand-shake protocols such as this are not desirable when the
communication takes place over packetized and fixed overhead transport mediums like Ethernet or
USB.
Bitscope command op-codes fall into two categories: simple commands for which a single reply
byte (the command itself) is returned, and complex commands where the reply byte is followed by
one or more data bytes (depending on the command).
The Network Adaptor allows multiple (simple) commands (and optionally one complex command)
to be grouped together and sent in a single Command Packet between the PC and the adaptor.
The adaptor feeds the commands to Bitscope, checking the reply byte returned for each one,
before sending a Reply Packet with all the acknowledgement bytes back to the PC.
If the last command in the group is a complex command, the data produced by the command is
appended to the reply. If more data than one packet is produced, multiple packets are returned.
COMMUNICATIONS CHANNELS
There are two bi-directional channels:

Control (Network Adaptor)

Data (Connected Bitscope)
The control channel is used to communicate with the Network Adaptor itself.
The data channel is used to communicate with the Bitscope connected to the adaptor.
Channels are identified by UDP Port.
The Data Channel is on port 0x4001 and the Control Channel on port 0x4002.
Control Channel
The use of the control channel is optional.
Its purpose is to allow the configuration of the IP address and other parameters as well as to obtain
status information. The Network Adaptor may be used in simple networks without ever needing to
use the control channel.
However, if required the Configuration Tool (for Windows or Linux with source) is available to
configure the adaptor via the control channel prior to use. Once configured, the adaptor stores this
information in FLASH memory so it need only be done once.
Data Channel
The data channel provides the means by which the PC application software (UAP) communicates
with its Network Bitscope(s). The UAP prepares a sequence of Bitscope commands and forwards
this sequence as a tagged Command Packet over the data channel.
The Network Adaptor passes the sequence of commands to Bitscope, one at a time with handshake,
and compiles the reply bytes into a Reply Packet which is returned to the UAP.
The Network Adaptor is transparent to the data path between the UAP on the PC and the connected
Bitscope with two exceptions; it concatenates bytes to support queued commands and it
prepends three protocol bytes to the Reply Packet.
PACKET FORMATS ( DATA CHANNEL )
There are two Bitscope Network packet formats:

Command (UAP to Bitscope)

Reply (Bitscope to UAP)
Both packet types are encapsulated as a UDP datagram payload.
Command Packet
The command packet consists of a single command ID (Cmd_ID) and 1 to 64 Bitscope Commands.
Cmd_ID is a sequence number that identifies the packet. It is returned in reply packet(s) to identify
the command packet that produced them.
The remaining 1 to 64 bytes are the sequence of command bytes passed to Bitscope itself.
Reply Packet Format
All but the last of these must be a simple command (ie, produces a single reply byte from
Bitscope).
Reply Packet
The reply packet comprises Network Adaptor ID (LIA_ID), command ID (Cmd_ID), reply ID
(Data_Seq) and 1 to 95 Bitscope data bytes.
The LIA_ID identifies which (of many) Network Bitscopes is replying.
The Cmd_ID identifies which command packet produced the reply packet. The Data_Seq identifies
which reply packet it is (if more than one is produced for a given command packet). The remaining
1 to 95 bytes comprise the sequence of Bitscope reply bytes and upload data produced by the
connected Bitscope.
CONFIGURING NETWORK BITSCOPE
The Network Adaptor Configuration Tool uses UDP multicast for plug and play operation.
This means you do not need to know the IP address of a Network Bitscope to configure it, nor do
you need to assign one to use it.
The multicast address used to "discover" Network Bitscopes is 230.10.10.10. Click on the
screenshot to the right to see the typical sequence of events as the configuration tool locates
available Bitscope(s).
If only one Bitscope is connected on the same network segment as the PC, there is no need to even
run the configuration tool as the network adaptor's multicast address can be used to communicate
with the Network Bitscope directly.
If more than one Bitscope is connected, multicast may still be used, but in this case each Bitscope
must be assigned a unique LIA_ID using the configuration tool (or other compatible software).
If you need to communicate with Network Bitscopes through a gateway on another network or
even half way around the world via the Internet, you can use the adaptor's configurable Unicast
address.
NETWORK BITSCOPE PROGRAMMING
Network Bitscope programming is essentially the same as regular Bitscope programming.
The main differences are that now you can:

Talk to multiple Bitscopes from one PC.

Use a multiple Bitscopes simultaneously
to create one large "Virtual Bitscope".

Use the universal Socket Programming interface instead of serial drivers.

Acquire captured data much faster than before.
To get you started we've provided the source project (Borland Delphi 6) for the Network
Configuration Tool which uses the Indy communications components for network communications.
Also available is a Borland C++Builder project demonstrating the use of the standard BSD Sockets
Interface written in C. Socket libraries exist for all major operating systems including Windows
and Linux. If you write in C/C++ but don't use Borland Tools, you should still the examples useful.
Also, a quick quide explaining what Sockets are and how they're used is available here.