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Done by Zahra Farhood
Done by Zahra Farhood
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Mainframe
Mainframe
Mainframe
Mainframe
Mainframe
Mainframe
Mainframe
definition
Workloads
Operating Systems
Hardware Design
Clustering
Physical & Virtual Storage
Registers
Done by Zahra Farhood
big iron that occupies 200
to 1000 square meters
room filled of I/O devices.
This room requires large
amounts of electrical
power and airconditioning to cool up
the equipments that cost
million of dollars.
Done by Zahra Farhood
powerful computers
supporting
thousands of
applications,
input/output devices
and supporting
thousands of users
simultaneously.
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Central processor
complex (CPC)
physical collection of
hardware that includes
main storage, one or
more central
processors, timers,
and channels.
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Batch Processing: a running mainframe process that does not need
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Online Transaction Processing (OTLP): a running transaction
user interaction
process that occurs interactively with the end user
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Batch processing Vs OTLP processing
Type of Workload
Data size
Record Size
Output
OTLP processing
Small
Small
Small
Batch processing
Large
Large
Large
Type of Workload
OTLP processing
Large numbers of users involved in
large numbers of transactions
Batch processing
Generating information for large
numbers of users or data entities
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popular mainframes operating system
include
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z/OS
z/VM
z/VSE
Linux for zSeries
z/TPF
Mainframes can run multiple
combinations of operating system
in the same platform.
Done by Zahra Farhood
z/Virtual Machine (z/VM) : consists of two vital parts: a control
program (CP) and a single-user operating system, CMS.
CP runs other operating systems as a guests systems in the virtual
machines it creates forming a hypervisor and ensures data and
application security among the guest systems.
CMS runs in a virtual machine and provides both an interactive end user
interface and the general z/VM application programming interface.
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z/Virtual Storage Extended (z/VSE): a common operating
system (64-bit addressing)used by small mainframes users . It provides
a smaller, less complex base for multiple batch processing (running in
parallel) and transaction processing. In addition to that, it suited for
processing large, complex workloads, such as those that require many
I/O operations, access to large amounts of data, or comprehensive
security.
users use the z/VM operating system to act as general terminal interface
for z/VSE application development and system management. If the
capabilities of z/VSE became unsuitable for there extensive needs they
can migrate to z/OS.
Done by Zahra Farhood
z/VSE design
Done by Zahra Farhood
z/VSE design:
◦ An address space describes the virtual storage addressing
range available to an online user or a running program.
◦ Two types of physical storage are available: central storage
(real storage) and auxiliary storage (AUX).
◦ z/VSE moves programs and data between central storage and
auxiliary storage through processes called paging.
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z/VSE design:
◦ z/VSE dispatches work for execution selecting programs to be
run based on priority and ability to execute and then restores
the program's status. All program instructions and data must be
in central storage when executing.
◦ An extensive set of facilities manages files stored on direct
access storage devices (disks) or tape cartridges.
◦ System operators use consoles to start and stop z/VSE, enter
commands, and manage the operating system.
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Linux for zSeries: a collection of Linux operating system compiled
to run on IBM mainframes such as Linux for S/390 (31 bit
addressing and 32 bit registers) and Linux for zSeries (64 bit
addressing and registers).
Linux on zSeries cannot share data with with the other operating
system exist in the same mainframe. Linux system under z/VM
can be quickly cloned to make another, separate Linux image.
The z/VM emulated LAN can be used to connect multiple Linux
images and to provide an external LAN route for them where
Read-only file systems, such as a typical /user file system, can be
shared by Linux images.
Done by Zahra Farhood
z/Transaction Processing Facility (z/TPF): is an IBM real-time,
high availability operating system designed to provide quick
response times to high volumes of messages from large networks
of terminals and workstations.
z/TPF used by corporations with very fast, high transaction
volume, such as credit card companies and airline reservation
systems.
z/TPF can use multiple mainframes in a loosely-coupled
environment to routinely handle tens of thousands of transactions
per second across large geographically dispersed networks,
while experiencing uninterrupted availability.
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z/TPF design
Done by Zahra Farhood
z/TPFdesign:
◦ The ESA/390 configuration for z/TPF system incorporates channel
subsystem and multiple central processing units (CPUs) that share
main storage. Multiple ESA configurations can be interconnected
through ESA channel-to-channel (CTC) communication. In a fiber
optic channel environment, an Enterprise Systems Connection
(ESCON) channel, operating in CTC mode, supports the CTC
communication.
◦ The central processing complex (CPC) denotes an ESA configuration
that is attached through locally attached channel subsystems to a set
of devices or other ESA configurations. Terminals and workstations
are attached to a central processing complex (CPC) through wide
area communication facilities which take the two forms:
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z/TPFdesign:
◦ private lines: leased communications channels for z/TPF system
exclusive use . Terminal concentrators are attached forming a private
network.
◦ Local access lines : leased lines attached to a common
communication carrier data network that is shared with other
enterprises. Terminal concentrators are attached to remote access
points. The management of the long distance routing and
transmission is the responsibility of the common carrier
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z/OS : a widely used mainframe operating system that can handle
many thousands of programs and interactive users concurrently.it
designs offer a stable, secure, and continuously available
environment for applications running on the mainframe.
z/OS design:
In most early operating systems, requests for work entered the
system one at a time. The operating system processed each
request or job as a unit, and did not start the next job until the
one being processed had completed.
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z/OS design:
But often a job had to wait for information to be read in from, or
written out to, a device such as a tape drive or printer. Input and
output (I/O) take a long time compared to the electronic speed of the
processor which leave the processor in the idle state.
To keep the processor working while a job waited z/OS dividing a job
into pieces and giving portions of the job to various system
components and subsystems that function interdependently. At any
point in time, one component or another gets control of the processor,
makes its contribution, and then passes control along to a user
program or another component.
Done by Zahra Farhood
Early system design:
Done by Zahra Farhood
Early system design:
The central processor contains the processors, memory, control
circuits, and interfaces for channels.
Channels connect to control units .A channel provides an
independent data and control path between I/O devices and memory.
Early systems had up to 16 channels.
A control unit contains logic to work with a particular type of I/O
device. For example, a control unit for a printer would have much
different internal circuitry and logic than a control unit for a tape drive.
Some control units can have multiple channel connections providing
multiple paths to the control unit and its devices.
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Early system design:
A parallel channel can be connected to a maximum of eight control
units. Each channel, control unit, and device has an address,
expressed as a hexadecimal number.
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Early system design:
The disk drive marked with an X has address 132 derived.
The disk drive marked with a Y in the figure can be addressed as
171, 571, or 671 because it is connected through three channels.
By convention the device is known by its lowest address (171), but all
three addresses could be used by the operating system to access the
disk drive.
When an application wants to access disk 171, the operating system
will first try channel 1. If it is busy (or not available), it will try channel
5, and so forth.
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Current system design:
Today's mainframe designs are more complex than early design , the
differences include:
◦ Parallel channels are not available on the newest mainframes and
are slowly being displaced on older systems.
◦ Parallel channels have been replaced with ESCON (Enterprise
Systems Connection) and FICON (Fiber Connection) channels.
These channels connect to only one control unit or, more likely, are
connected to a director (switch) and are optical fibers.
Done by Zahra Farhood
Current system design:
◦ Current mainframes have more than 16 channels ( over 1000
channels)and use two hexadecimal digits as the channel portion of an
address.
◦ Channels are generally known as CHPIDs (channel path identifiers)
or PCHIDs (physical channel identifiers) on later systems. The
channels are all integrated in the main processor box.
◦ Current CPC designs are considerably more complex than the early
S/360 design.
Done by Zahra Farhood
Current system design: I/O connectivity
Done by Zahra Farhood
Current system design: I/O connectivity
partitions create separate logical machines in the central processor
complex (CPC). ESCON and FICON channels are logically similar to
parallel channels but they use fiber connections and operate much
faster.
A modern system might have 100-200 channels or channel path
identifiers (CHPIDs).
ESCON and FICON channels connect to only one device or one port
on a switch.
Done by Zahra Farhood
Current system design: I/O connectivity
Most modern mainframes use switches between the channels and
the control units. The switches may be connected to several systems,
sharing the control units and some or all of its I/O devices across all
the systems.
CHPID addresses are two hexadecimal digits. Multiple partitions can
sometimes share CHPIDs. An I/O subsystem layer exists between
the operating systems in partitions and the CHPIDs.
An ESCON director or FICON switch is a device that can sustain high
data rates through many connections. (A large director might have
200 connections, for example, and all of these can be passing data at
the same time.)
Done by Zahra Farhood
Current system design: I/O connectivity
The director or switch must keep track of which CHPID (and partition)
initiated which I/O operation so that data and status information is
returned to the right place. Multiple I/O requests, from multiple
CHPIDs attached to multiple partitions on multiple systems, can be in
progress through a single control unit.
The I/O control layer uses a control file known as an IOCDS (I/O
Control Data Set) that translates physical I/O addresses (composed
of CHPID numbers, switch port numbers, control unit addresses, and
unit addresses) into device numbers that are used by the operating
system software to access devices.
Done by Zahra Farhood
Current system design: I/O connectivity
This is loaded into the Hardware Save Area (HSA) at power-on and can
be modified dynamically. A device number looks like the addresses for
early S/360 machines except that it can contain three or four
hexadecimal digits.
Today's mainframes have two layers of I/O address translations
between the real I/O elements and the operating system software. The
second layer was added to make migration to newer systems easier.
Modern control units, especially for disks, often have multiple channel
(or switch) connections and multiple connections to their devices. They
can handle multiple data transfers at the same time on the multiple
channels. Each device will have a unit control block (UCB) in each
z/OS image.
Done by Zahra Farhood
Current system design: I/O connectivity
Done by Zahra Farhood
Current system design: System control and partitioning
Among the system control functions is the capability to partition the
system into several logical partitions (LPARs). An LPAR contains
resources (processors, memory, input/output devices), its own copy of
operating system, and has its own operator and operates as an
independent system.
Multiple logical partitions can exist within a mainframe hardware
system.Years ago, a limit of 15 LPARs in a mainframe, recent machines
have 30 (and potentially more). Practical limitations of memory size, I/O
availability, and available processing power usually limit the number of
LPARs to less than these maximums.
Done by Zahra Farhood
Current system design: System control and partitioning
The hardware and firmware that provides partitioning is known as
PR/SM (Processor Resource/System Manager). It is the PR/SM
functions that are used to create and run LPARs.
System administrators assign portions of memory to each LPAR;
memory cannot be shared among LPARs. The administrators can
assign processors to specific LPARs or they can allow the system
controllers to dispatch any or all the processors to all the LPARs using
an internal load-balancing algorithm.
Channels (CHPIDs) can be assigned to specific LPARs or can be
shared by multiple LPARs, depending on the nature of the devices on
each channel.
Done by Zahra Farhood
Current system design: System control and partitioning
Partitioning control specifications are partly contained in the IOCDS and
are partly contained in a system profile. The IOCDS and profile both
reside in the Support Element (SE) which is simply a notebook
computer inside the system. The SE can be connected to one or more
Hardware Management Consoles (HMCs), which are desktop personal
computers used to monitor and control hardware such as the mainframe
microprocessors.
In a mainframe system with three LPARs, for example, you might have a
production z/OS in LPAR1, a test version of z/OS in LPAR2, and Linux
for S/390 in LPAR3. If this total system has 8 GB of memory, we might
have assigned 4 GB to LPAR1, 1 GB to LPAR2, 1 GB to LPAR3, and
have kept 2 GB in reserve. The operating system consoles for the two
z/OS LPARs might be in completely different locations.
Done by Zahra Farhood
Current system design: System control and partitioning
Done by Zahra Farhood
Current system design: System processing units
Today's IBM mainframes have a central processor complex (CPC).
Each processor contains the sequencing and processing facilities for
instruction execution, interruption action, timing functions, initial program
loading, and other machine related functions.
Processing may be in parallel or in series; the width of the processing
elements, the multiplicity of the shifting paths, and the degree of
simultaneity in performing the different types of arithmetic differ from
one model of processor to another without affecting the logical results.
Instructions which the processor executes fall into eight classes:
general, decimal, floating point support (FPS), binary floating point
(BFP), decimal floating point (DFP), hexadecimal floating point (HFP),
control, and I/O instructions.
Done by Zahra Farhood
Current system design: System processing units
The central processor complex (CPC) may contain several different
types of z/Architecture processors that can be used for slightly different
purposes.
Each processor is characterized by IBM. The potential
characterizations are:
◦ (CP) : This processor type is available for normal operating system and
application software.
◦ System Assistance Processor (SAP) : The SAPs execute internal code
to provide the I/O subsystem. A SAP, for example, translates device
numbers and real addresses of channel path identifiers (CHPIDs),
control unit addresses, and device numbers. It manages multiple paths
to control units and performs error recovery for temporary errors.
Done by Zahra Farhood
Current system design: System processing units
◦ Integrated Coupling Facility (ICF) : A coupling facility is, in effect, a large
memory scratch pad used by multiple systems to coordinate work. ICFs
must be assigned to LPARs that then become coupling facilities.
◦ Spare : An uncharacterized PU functions as a "spare." If the system
controllers detect a failing CP or SAP, it can be replaced with a spare
PU.
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Current system design: System disk devices
IBM 3390 disk drives are commonly used on current mainframes.
Conceptually, the associated control unit (3990) typically has four
channels connected to one or more processors (probably with a switch),
and the 3390 unit typically has eight or more disk drives.
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Current system design: System disk devices
The current equivalent device is an IBM 2105 Enterprise Storage Server
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Current system design: System disk devices
The 2105 emulates a large number of control units and 3390 disk drives.
It contains up to 11 TB of disk space, has up to 32 channel interfaces, 16
GB cache, and 284 MB of non-volatile memory (used for write queueing).
The Host Adapters appear as control unit interfaces and can connect up to
32 channels (ESCON or FICON). The physical disk drives are commodity
SCSI-type units (although a serial interface, known as SSA, is used to
provide faster and redundant access to the disks).
The internal processing (to emulate 3990 control units and 3390 disks) is
provided by four high-end RISC processors in two processor complexes. A
separate console is used to configure and manage the unit. The 2105
offers many functions not available in real 3390 units, including
FlashCopy, Extended Remote Copy, Concurrent Copy, Parallel Access
Volumes.
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Parallel Sysplex
This technology allows the linking of up to 32 servers with nearly linear
scalability to create a powerful commercial processing clustered system.
As a result, work requests that are associated with a single workload
dynamically distributed for parallel execution on nodes in the sysplex
cluster based on available processor capacity. Every server in a Parallel
Sysplex cluster has access to all data resources, and every "cloned"
application can run on every server.
Parallel Sysplex provides a "shared data" clustering technique that permits
multisystem data sharing with high performance read/write integrity.
Sysplex design characteristics help businesses to run continuously, even
during periods of dramatic change. Sysplex sites can dynamically add and
change systems in a sysplex, and configure the systems for no single
points of failure.
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Parallel Sysplex
Done by Zahra Farhood
Parallel Sysplex
A Parallel Sysplex relies on one or more coupling facilities (CFs). A
coupling facility is a mainframe processor, with memory and special
channels, and a built-in operating system. It has no I/O devices, other than
the special channels, and the operating system is very small. A CF
functions largely as a fast scratch pad. It is used for three purposes:
◦ Locking information that is shared among all attached systems
◦ Cache information (such as for a database) that is shared among all
attached systems
◦ Data list information that is shared among all attached systems
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Conceptually, mainframes and all other computers have two types of
physical storage: Internal and external. Physical storage located on the
mainframe processor itself(processor storage or real storage) Physical
storage external to the mainframe, including storage on direct access
devices, such as disk drives and tape drives. This storage is called paging
storage or auxiliary storage.
The primary difference between the two kinds of storage relates to the way
in which it is accessed, as follows:
Central storage is accessed synchronously with the processor. That is, the
processor must wait while data is retrieved from central storage. Auxiliary
storage is accessed asynchronously. The processor accesses auxiliary
storage through an input/output (I/O) request, which is scheduled to run
amid other work requests in the system. During an I/O request, the
processor is free to execute other, unrelated work.
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As with memory for a personal computer, mainframe central storage is
faster than auxiliary storage due to its location in processor itself.
In z/OS, each user has access to virtual storage, rather than physical
storage. This use of virtual storage is central to the unique ability of z/OS
to interact with large numbers of users concurrently, while processing the
largest workloads.
With the release of zSeries mainframes in 2000, IBM extended the
addressability of the architecture from 31 to 64 bits. With 64-bit
addressing, the potential size of a z/OS address space expands to a vast
size. Each address space, called a 64-bit address space, is 16 exabytes
(EB) in size; an exabyte is slightly more than one billion gigabytes. The
new address space has logically 264 addresses. It is 8 billion times the
size of the former 2-gigabyte address space, which allows a program to
address up 18,446,744,073,709,600,000 bytes.
Done by Zahra Farhood
Done by Zahra Farhood
To address the high virtual storage available with the 64-bit architecture,
the program uses 64-bit-specific instructions. Although the architecture
introduces unique 64-bit exploitation instructions, the program can use
both 31-bit and 64-bit instructions, as needed.
For compatibility, the layout of the storage areas for an address space is
the same below 2 gigabytes, providing an environment that can support
both 24-bit and 31-bit addressing. The area that separates the virtual
storage area below the 2-gigabyte address from the user private area is
called the bar. The user private area is allocated for application code
rather than operating system code.
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Done by Zahra Farhood
In a 16-exabyte address space with 64-bit virtual storage addressing,
there are three additional levels of translation tables, called region tables:
Region third table (R3T), region second table (R2T), and region first table
(R1T). The region tables are 16 KB in length, and there are 2048 entries
per table. Each region has 2 GB.
Segment tables and page table formats remain the same as for virtual
addresses below the bar. When translating a 64-bit virtual address, once
the system has identified the corresponding 2-GB region entry that points
to the segment table, the process is the same as that described
previously.
Done by Zahra Farhood
To allow each user to act as though this much storage really exists in the
computer system, z/OS keeps only the active portions of each program in
central storage. It keeps the rest of the code and data in files called page
data sets on auxiliary storage, which usually consists of a number of highspeed direct access storage devices (DASD). By bringing pieces of the
program into central storage only when the processor is ready to execute
them, z/OS can execute more and larger programs concurrently.
For a processor to execute a program instruction, both the instruction and
the data it references must be in central storage. The convention of early
operating systems was to have the entire program reside in central
storage when its instructions were executing. Instead, by bringing pieces
of the program into central storage only when the processor is ready to
execute them moving them out to auxiliary storage when it doesn't need
them, an operating system can execute more and larger programs
concurrently.
Done by Zahra Farhood
To allow each user to act as though this much storage really exists in the
computer system, z/OS keeps only the active portions of each program in
central storage. It keeps the rest of the code and data in files called page
data sets on auxiliary storage, which usually consists of a number of highspeed direct access storage devices (DASD). By bringing pieces of the
program into central storage only when the processor is ready to execute
them, z/OS can execute more and larger programs concurrently.
For a processor to execute a program instruction, both the instruction and
the data it references must be in central storage. The convention of early
operating systems was to have the entire program reside in central
storage when its instructions were executing. Instead, by bringing pieces
of the program into central storage only when the processor is ready to
execute them moving them out to auxiliary storage when it doesn't need
them, an operating system can execute more and larger programs
concurrently.
Done by Zahra Farhood
Dynamic address translation is the process of translating a virtual address
during a storage reference into the corresponding real or absolute
address. The virtual address may be a primary virtual address, secondary
virtual address.
These addresses are translated by means of the primary, the secondary,
respectively. After selection of the appropriate address-space-control
element, the translation process is the same for the two types of virtual
address.
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An address-space-control element may be a segment-table designation
specifying a 2G-byte address space, a region-table desigation. A segmenttable designation or region-table designation causes translation to be
performed by means of tables established by the operating system in real
or absolute storage.
A virtual address, accordingly, is divided into four principal fields: Bits 0-32
are called the region index (RX), bits 33-43 are called the segment index
(SX), bits 44-51 are called the page index (PX), and bits 52-63 are called
the byte index (BX).
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a virtual address space can be a 2-gigabyte space consisting of one
region, or as large as a 16-exabyte space. The RX part of a virtual
address for a 2-gigabyte address space must be all zeros; otherwise, an
exception is recognized.
The RX part of a virtual address is itself divided into three fields. Bits 0-10
are called the region first index (RFX), bits 11-21 are called the region
second index (RSX), and bits 22-32 are called the region third index
(RTX). Bits 0-32 of the virtual address have the format shown .
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A virtual address in which the RTX is the left most significant part (a 42-bit
address) is capable of addressing 4 terabytes (4096 regions), one in which
the RSX is the left most significant part (a 53-bit address) is capable of
addressing 8 petabytes (four million regions), and one in which the RFX is
the left most significant part (a 64-bit address) is capable of addressing 16
exabytes (8 billion regions).
A virtual address in which the RX is always zero can be translated into real
addresses by means of one or two translation tables, as follows:
the virtual address can be translated by means of a segment table and a
page table.
the virtual address can be translated by means of a segment table only.
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If the RX may be nonzero, from one to three additional translation tables
are required, as follows. If the RFX may be nonzero, a region first table,
region second table, and region third table are required. If the RFX is
always zero but the RSX may be nonzero, a region second table and
region third table are required. If the RFX and RSX are always zero but
the RTX may be nonzero, a region third table is required. An exception is
recognized if the address-space-control element for an address space
does not designate the highest level of table (beginning with the region
first table and continuing downward to the segment table) needed to
translate a reference to the address space.
Done by Zahra Farhood
The operating system can divide a program into pieces the size of frames
or slots and assign each piece a unique address. This arrangement allows
the operating system to keep track of these pieces. In z/OS, the program
pieces are called pages.
Pages are referenced by their virtual addresses and not by their real
addresses. From the time a program enters the system until it completes,
the virtual address of the page remains the same, regardless of whether
the page is in central storage or auxiliary storage. Each page consists of
individual locations called bytes, each of which has a unique virtual
address.
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z/OS is performing paging for a program running in virtual storage. The
lettered boxes represent parts of the program. In this simplified view,
program parts A, E, F, and H are active and running in central storage
frames, while parts B, C, D, and G are inactive and have been moved to
auxiliary storage slots. All of the program parts, however, reside in virtual
storage and have virtual storage addresses.
Done by Zahra Farhood
z/OS uses a series of tables to determine whether a page is in real or
auxiliary storage, and where. To find a page of a program, z/OS checks
the table for the virtual address of the page, rather than searching through
all of physical storage for it.
To select pages for paging out to auxiliary storage, z/OS follows a "Least
Used" algorithm. That is, z/OS assumes that a page that has not been
used for some time will probably not be used in the near future.
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Many programs and users are competing for the use of the system. So
how does z/OS preserves the integrity of each user's work? One
technique is through the use of multiple storage protect keys.
Under z/OS, the information in central storage is protected from
unauthorized use by means of multiple storage protect keys. A control field
in storage called a key is associated with each 4K frame of central
storage.
When a request is made to modify the contents of a central storage
location, the key associated with the request is compared to the storage
protect key. If the keys match or the program is executing in key 0, the
request is satisfied. If the key associated with the request does not match
the storage key, the system rejects the request and issues a program
exception interruption.
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Moreover, z/OS uses 16 storage protect keys. . The key is stored in bits 8
through 11 of the program status word (PSW). A PSW is assigned to each
job in the system.
The program status word (PSW) is a 128-bit data area in the processor
that, along with a variety of other types of registers (control registers,
timing registers, and prefix registers) provides details crucial to both the
hardware and the software. The current PSW includes the address of the
next program instruction and control information about the program that is
running. Each processor has only one current PSW. Thus, only one task
can execute on a processor at a time.
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The PSW controls the order in which instructions are fed to the processor,
and indicates the status of the system in relation to the currently running
program.
When an interruption occurs, the CPU places the current PSW in an
assigned storage location, called the old-PSW location, for the particular
class of interruption. The CPU fetches a new PSW from a second
assigned storage location. This new PSW determines the next program to
be executed. When it has finished processing the interruption, the program
handling the interruption may reload the old PSW, making it again the
current PSW, so that the interrupted program can continue.
There are six classes of interruption: external, I/O, machine check,
program, restart, and supervisor call. Each class has a distinct pair of oldPSW and new PSW locations permanently assigned in real storage.
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g
Done by Zahra Farhood
PER Mask (R): Bit 1 controls whether the CPU is enabled for interruptions
associated with program event recording (PER).
DAT Mode (T): Bit 5 controls whether implicit dynamic address translation
of logical and instruction addresses used to access storage takes place.
I/O Mask (IO): Bit 6 controls whether the CPU is enabled for I/O
interruptions.
Instruction Address: Bits 64-127 of the PSW are the instruction address.
This address designates the location of the leftmost byte of the next
instruction to be executed; unless the CPU is in the wait state (bit14 of the
PSW is one). Bit positions 0, 2-4, 24-30, and 33-63 are unassigned and
must contain zeros. A specification exception is recognized when these bit
positions do not contain zeros.
Done by Zahra Farhood
Mainframe architecture provides registers to keep track of things. The
PSW, for example, is a register used to contain information that is required
for the execution of the currently active program. Other registers
Mainframes provide
Done by Zahra Farhood
Mainframe architecture provides registers to keep track of things. The
PSW, for example, is a register used to contain information that is required
for the execution of the currently active program. Other registers
Mainframes provide
Done by Zahra Farhood
Access Registers
These 16 registers with 32 bit wide specify the address space in which
data is found. Access register 0 always designates the current instruction
space. When one of access registers 1-15 is used to designate an
address space, the CPU determines which address space is designated
by translating the contents of the access register. When access register 0
is used to designate an address space, the CPU treats the access register
as designating the current instruction space, and it does not examine the
actual contents of the access register. Therefore, the 16 access registers
can designate, at any one time, the current instruction space and a
maximum of 15 other spaces.
Done by Zahra Farhood
General Registers
These 16 registers with 64 bit wide address data in storage, and also hold
user data. The general registers may be used as base-address registers
and index registers in address arithmetic and as accumulators in general
arithmetic and logical operations. The general registers are identified by
the numbers 0-15 and are designated by a four-bit R field in an instruction.
an instruction B or R field designates an access register, for use in accessregister translation, under the following conditions: The field is a B field
which designates a general register containing a base address. The base
address is used, along with a displacement (D) and possibly an index (X),
to form the logical address of a storage operand. The field is an R field
which designates a general register containing the logical address of a
storage operand.
Done by Zahra Farhood
General Registers
Some instructions provide for addressing multiple general registers by
having several R fields. For some instructions, the use of a specific
general register is implied rather than explicitly designated by an R field of
the instruction. For some operations, either bits 32-63 or bits 0-63 of two
adjacent general registers are coupled, providing a 64-bit or 128-bit
format, respectively.
In these operations, the program must designate an even-numbered
register, which contains the leftmost (high order) 32 or 64 bits. The next
higher-numbered register contains the rightmost (low-order) 32 or 64 bits.
In addition to their use as accumulators in general arithmetic and logical
operations, 15 of the 16 general registers are also used as base-address
and index registers in address generation.
Done by Zahra Farhood
General Registers
In these cases, the registers are designated by a four-bit B field or X field
in an instruction. A value of zero in the B or X field specifies that no base
or index is to be applied, and, thus, general register 0 cannot be
designated as containing a base address or index.
Floating Point Register
These 16 registers hold numeric data in floating point form. All floating
point instructions use the same set of floating point registers.
The floating point registers are identified by the numbers 0 15 and are
designated by a four bit R field in floating point instructions.
Done by Zahra Farhood
Floating Point Register
Each floating point register is 64 bits long and can contain either a short
(32 bit) or a long (64 bit) floating point operand. As shown in Fig.23, pairs
of floating point registers can be used for extended (128 bit) operands.
Each of the eight pairs is referred to by the number of the lower numbered
register of the pair.
Done by Zahra Farhood
Control Registers
These registers are used by the operating system itself, for example, as
references to translation tables. Each control register has 64 bit positions.
The bit positions in the registers are assigned to particular facilities in the
system, such as program-event recording, and are used either to specify
that an operation can take place or to furnish special information required
by the facility. The control registers are identified by the numbers 0-15 and
are designated by four-bit R fields in the instructions LOAD CONTROL
and STORE CONTROL. Multiple control registers can be addressed by
these instructions.
Done by Zahra Farhood
Done by Zahra Farhood
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Wikipedia.(2010, April 28). Mainframe computer [Online]. Available:
http://en.wikipedia.org/wiki/Mainframe_computer
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ic=/diricinfo/vsd0_c_zvm.html
Mike Ebbers, Wolfgang Bosch, Hans Joachim Ebert, Helmut Hellner, Jerry Johnston,
Wilhelm Mild et.al.,“Introduction to the New Mainframe: z/VSE Basics,” International
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IBM, “z/Architecture Principles of Operation,” International Technical Support
Organization, Vol.7, pp.20–1100, February 2008.
Done by Zahra Farhood
Done by Zahra Farhood