Download Slide 1 - Oxford University Press

Survey
yes no Was this document useful for you?
   Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

page
1
page
2
page
3
page
4
page
5
page
6
page
7
page
8
page
9
page
10
page
11
page
12
page
13
page
14
page
15
page
16
page
17
page
18
page
19
page
20
page
21
page
22
page
23
page
24
page
25
page
26
Document related concepts
no text concepts found
Transcript 
Figure B.93 Schematic capture of the Folded-Cascode amplifier.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.95 Schematic capture of the two-stage CMOS op amp.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.97 Frequency response of the two–stage CMOS op-amp amplifier.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.98 Schematic capture of the A circuit.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.99 Schematic capture of the A- circuit.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.100 Schematic capture of the closed-loop circuit.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.101 Frequency response of the closed-loop circuit.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.102 Schematic capture of class B output stage.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.103 Load voltage, current, and instantaneous and average load power.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.104 Supply voltage, current, and instantaneous and average supply power.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.105 Voltage, current, and instantaneous and average power for Qp.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.106 VTC of class B output stage.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.107 Fourier-series components of the output voltage and class B output stage THD.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.108 Schematic capture of the two-stage CMOS op amp.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.109 Magnitude and phase response of the op-amp circuit with R = 1.53 k, CC = 0 (no frequency compensation),
and CC = 1.8 pF (PM = 75o).
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.113 Large-signal step response (for a 2.2-V step input) if the op-amp circuit is connected in a unity-gain
configuration. The slope of the rising and falling edges of the output waveform correspond to the slew rate of the op amp.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.114 Schematic capture of the CMOS inverter.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.115 Time domain response of the CMOS inverter to measure tPHL.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.116 Output voltage versus input voltage for the inverter (to measure low and high
noise margins NML and NMH).
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.117 Output voltage versus input voltage for the inverter (to the threshold voltage measure Vth).
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Figure B.118 Supply current versus input voltage for the inverter.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Related documents