Download Lecture 3 Two-Level Logic Minimization

Lecture 4
Combinational Logic Implementation
Technologies
Hai Zhou
ECE 303
Advanced Digital Design
Spring 2002
ECE C03 Lecture 4
1
Outline
•
•
•
•
•
•
Review of Combinational Logic Technologies
Programmable Logic Devices (PLA, PAL)
MOS Transistor Logic
Multiplexers/Decoders
ROM
READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4,
5.5 5.6, 5.7, 6.2
ECE C03 Lecture 4
2
Programmable Arrays of Logic Gates
• Until now, we learned about designing Boolean
functions using discrete logic gates
• We will now describe a technique to arrange AND
and OR gates (or NAND and NOR gates) into a
general array structure
• Specific functions can be programmed
• Can use programmable logic arrays (PLA) or
programmable array logic (PAL)
ECE C03 Lecture 4
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PALs and PLAs
Pre-fabricated building block of many AND/OR gates (or NOR, NAND)
"Personalized" by making or breaking connections among the gates
Programmable Array Block Diagram for Sum of Products Form
Inputs
Dens e array of
AND gates
Produc t
terms
Dens e array of
OR gates
Outputs
ECE C03 Lecture 4
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Why PALs/PLAs Work
Equations
Example:
F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Personality Matrix
Produc t
term
AB
BC
AC
BC
A
Inputs
A B C
1 1 - 0 1
1 - 0
- 0 0
1 - -
Outputs
F0 F1 F2 F3
0 1 1 0
0 0 0 1
0 1 0 0
1 0 1 0
1 0 0 1
Key to Success: Shared Product Terms
Input Side:
1 = asserted in term
0 = negated in term
- = does not participate
Output Side:
1 = term connected to output
Reus e
0 = no connection to output
of
terms
ECE C03 Lecture 4
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Example of PALs and PLAs
All possible connections are available
before programming
ECE C03 Lecture 4
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Example of PALs and PLAs (Contd)
Unwanted connections are "blown"
Note: some array structures
work by making connections
rather than breaking them
ECE C03 Lecture 4
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Alternative Representations
Short-hand notation
so we don't have to
draw all the wires!
Notation for implementing
F0 = A B + A' B'
F1 = C D' + C' D
ECE C03 Lecture 4
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Design Example
Multiple functions of A, B, C
ABC
A
F1 = A B C
B
F2 = A + B + C
C
A
F3 = A B C
B
F4 = A + B + C
C
F5 = A xor B xor C
ABC
ABC
F6 = A xnor B xnor C
ABC
ABC
ABC
ABC
ABC
ECE C03 Lecture 4
F1
F2
F3
F4 F5
F6
9
Differences Between PALs and PLAs
PAL concept — implemented by Monolithic Memories
constrained topology of the OR Array
A given column of the OR array
has access to only a subset of
the possible product terms
PLA concept — generalized topologies in AND and OR planes
ECE C03 Lecture 4
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Design Example: BCD-to-Gray Code
Converter
Truth Table
K-maps
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X
Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X
Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X
A
AB
00
01
11
10
00
0
0
X
1
01
0
1
X
1
11
0
1
X
X
10
0
1
X
X
CD
A
AB
00
01
11
10
00
0
1
X
0
01
0
1
X
0
11
0
0
X
X
10
0
0
X
X
CD
D
C
C
B
B
K-map for W
K-map for X
A
AB
A
AB
00
01
11
10
00
0
1
X
0
01
0
1
X
0
11
1
1
X
X
CD
Minimized Functions:
D
00
01
11
10
00
0
0
X
1
01
1
0
X
0
11
0
1
X
X
10
1
0
X
X
CD
D
C
W=A+BD+BC
X = B C'
Y=B+C
Z = A'B'C'D + B C D + A D' + B' C D'
D
C
10
1
1
X
X
B
B
K-map for Y
K-map for Z
ECE C03 Lecture 4
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Programmed PAL
0
0
0
0
0
0
ABCD
ECE C03
4 product terms per each
ORLecture
gate4
12
Non-Gate Logic
So far we have seen:
AND-OR-Invert
PAL/PLA
Generalized Building Blocks
Beyond Simple Gates
Kinds of "Non-gate logic":
• switching circuits built from CMOS transmission gates
• multiplexer/selecter functions
• decoders
• tri-state and open collector gates
• read-only memories
ECE C03 Lecture 4
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Steering Logic: Switches
Voltage Controlled Switches
Gate
Channel
Region
Oxide
Source
Drain
Silicon Bulk
n-type Si
p-type Si
"n-Channel MOS"
Metal Gate, Oxide, Silicon Sandwich
Diffusion regions: negatively charged ions driven into Si surface
Si Bulk: positively charged ions
By "pulling" electrons to the surface, a conducting channel is
formed
ECE C03 Lecture 4
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Switching or Steering Logic
Voltage Controlled Switches
Gate
Source
Drain
Logic 1 on gate,
Source and Drain connected
nMOS Transistor
Gate
Source
Logic 0 on gate,
Source and Drain connected
Drain
pMOS Transistor
ECE C03 Lecture 4
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Logic Gates with Steering Logic
Logic Gates from Switches
+5V
A
B
A
+5V
A
B
+5V
AB
A
A+B
Inverter
NAND Gate
NOR Gate
Pull-up network constructed from pMOS transistors
Pull-down network constructed from nMOS transistors
ECE C03 Lecture 4
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Inverter with Steering Logic
Inverter Operation
+5V
"1"
+5V
"0"
"0"
Input is 1
Pull-up does not conduct
Pull-down conducts
Output connected to GND
ECE C03 Lecture 4
"1"
Input is 0
Pull-up conducts
Pull-down does not conduct
Output connected to VDD
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NAND Gate with Steering Logic
NAND Gate Operation
"1"
"0"
"1"
+5V
"1"
+5V
"0"
A = 1, B = 1
Pull-up network does not conduct
Pull-down network conducts
Output node connected to GND
ECE C03 Lecture 4
"1"
A = 0, B = 1
Pull-up network has path to VDD
Pull-down network path broken
Output node connected to VDD
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NOR Gate with Steering Logic
NOR Gate Operation
"0"
"1"
"0"
+5V
"0"
+5V
"1"
A = 0, B = 0
Pull-up network conducts
Pull-down network broken
Output node at VDD
"0"
A = 1, B = 0
Pull-up network broken
Pull-down network conducts
Output node at GND
ECE C03 Lecture 4
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CMOS Transmission Gate
nMOS transistors good at passing 0's but bad at passing 1's
pMOS transistors good at passing 1's but bad at passing 0's
perfect "transmission" gate places these in parallel:
Control
Control
In
Out
Control
Switches
In
Control
Out
Control
Transistors
ECE C03 Lecture 4
In
Out
Control
Transmission or
"Butterfly" Gate
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Selection/Demultiplexing
S
Selector:
Choose I0 if S = 0
Choose I1 if S = 1
I
0
S
I
Z
S
1
S
S
Demultiplexer:
I to Z0 if S = 0
I to Z1 if S = 1
Z0
I
S
S
Z1
S
ECE C03 Lecture 4
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Use of Multiplexers or Demultiplexers
A
Demultiplexers
Y
Multiplexers
B
Z
A
Y
Demultiplexers
B
Multiplexers
Z
So far, we've only seen point-to-point connections among gates
Mux/Demux used to implement multiple source/multiple destination
interconnect
ECE C03 Lecture 4
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Well-formed Switching Logic
Problem with the Demux implementation:
multiple outputs, but only one connected to the input!
S
Z0
S
"0"
I
S
S
Z1
S
"0"
S
The fix: additional logic to drive every output to a known value
Never allow outputs to "float"
ECE C03 Lecture 4
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Use of Multiplexers/Selectors
Multi-point connections
A0
Sa
A1
B0
B1
MUX
MUX
A
B
Multiple input sources
Sb
Sum
Ss
Multiple output destinations
DEMUX
S0
S1
ECE C03 Lecture 4
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General Concept of Using Multiplexers
2
n
data inputs, n control inputs, 1 output
n
used to connect 2 points to a single point
control signal pattern form binary index of input connected to output
Z = A' I 0 + A I 1
A
0
1
Functional form
Logical form
ECE C03 Lecture 4
Z
I0
I1
I1
0
0
0
0
1
1
1
1
I0
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
Z
0
0
1
0
0
1
1
1
Two alternative forms
for a 2:1 Mux Truth Table
25
I0
Use
of
Multiplexers/Selectors
2:1
I1
mux
Z = A' I 0 + A I 1
Z
A
I0
I1
I2
I3
4:1
mux
A
I0
I1
I2
I3
Z
B
8:1
mux
I4
I5
I6
I7
A
Z = A' B' I0 + A' B I1 + A B' I2 + A B I3
B
Z
C
Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 +
A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7
n -1
2
In general, Z = S
m I
k=0
k k
in minterm shorthand form for a 2 n :1 Mux
ECE C03 Lecture 4
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Alternative Implementation
A
B
I0
Z
I1
I2
I3
Transmission Gate
Implementation of
4:1 Mux
Gate Level
Implementation
of 4:1 Mux
twenty transistors
thirty six transistors
ECE C03 Lecture 4
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Design of Large Multiplexers
Large multiplexers can be implemented by cascaded smaller ones
I0
I1
I2
I3
0 4:1
1 mux
2
3S S
I4
I5
I6
I7
0 4:1
1 mux
2
3S S
1
1
B
Control signals B and C simultaneously
choose one of I0-I3 and I4-I7
8:1
mux
0 2:1
mux
1 S
0
Z
Control signal A chooses which of the
upper or lower MUX's output to gate to Z
I0
0
I1
1 S
0
C
C
A
I2
0
I3
1 S
0
1
Alternative 8:1 Mux Implementation
C
I4
0
I5
1 S
C
I6
0
I7
1 S
ECE C03 Lecture 4
Z
2
3 S0
S1
A
B
28
C
2
Multiplexers/Selectors as General
Purpose Blocks
n-1
:1 multiplexer can implement any function of n variables
n-1 control variables; remaining variable is a data input to the mux
Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C
= A' B' (C') + A' B (C') + A B' (0) + A B (1)
1
0
1
0
0
0
1
1
0
1
2
3
4
5
6
7
F
8:1
MUX
S2 S1 S0
A
B
C
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
1
0
1
0
0
0
1
1
C
C
0
C
C
0
1
0
1
2
3
4:1
MUX
S1
A
F
S0
B
1
"Lookup Table"
ECE C03 Lecture 4
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Generalization of Multiplexer/Selector
Logic F
I I … I
1
n-1 Mux
control variables
single Mux
data variable
…
2
n
0
1
0
0
0
1
1
0
1
1
Four possible
configurations
of the truth table rows
0
In
In
1
Can be expressed as
a function of In, 0, 1
Example:
G(A,B,C,D) can be implemented by an 8:1 MUX:
K-map
Choose A,B,C
as control variables
Multiplexer
Implementation
TTL package efficient
May be gate inefficient
ECE C03 Lecture 4
1
D
0
1
D
D
D
D
0
1
2
3
4
5
6
7
G
8:1
mux
S2
A
S1
B
S0
C
30
Decoders/Demultiplexers
Decoder: single data input, n control inputs, 2
n
outputs
control inputs (called select S) represent Binary index of output to which
the input is connected
data input usually called "enable" (G)
1:2 Decoder:
O0 = G • S; O1 = G • S
3:8 Decoder:
O0 = G • S0 • S1 • S2
O1 = G • S0 • S1 • S2
2:4 Decoder:
O0 = G • S0 • S1
O2 = G • S0 • S1 • S2
O1 = G • S0 • S1
O3 = G • S0 • S1 • S2
O2 = G • S0 • S1
O4 = G • S0 • S1 • S2
O3 = G • S0 • S1
O5 = G • S0 • S1 • S2
O6 = G • S0 • S1 • S2
ECE C03 Lecture 4
O7 = G • S0 • S1 • S2
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Alternative Implementations
G
Output0
Select
/G
Select
Output0
Output1
Output1
1:2 Decoder, Active Low Enable
1:2 Decoder, Active High Enable
/G
G
Select0
Output0
Output0
Output1
Output1
Output2
Output2
Output3
Output3
Select0
Select1
2:4 Decoder, Active High Enable
Select1
2:4 Decoder, Active Low Enable
ECE C03 Lecture 4
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Switch Level Implementations
Select
Select
G
G
Output
0
Select
Select
Output
0
Select
Select
"0"
Select
Output
1
Select
Select
Output
1
Select
Naive, Incorrect Implementation
Select
All outputs not driven at all times
"0"
Select
Correct 1:2 Decoder Implementation
ECE C03 Lecture 4
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Switch Implementation of 2:4 Decoder
Select
G
0
Select
1
Output
0
Operation of 2:4 Decoder
"0"
"0"
G
S0 = 0, S1 = 0
Output
1
"0"
one straight thru path
three diagonal paths
"0"
G
Output
2
"0"
"0"
G
Output
3
"0"
"0"
ECE C03 Lecture 4
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Decoder as a Logic Building Block
Enb
3:8
dec
S2
A
S1
B
S0
0
1
2
3
4
5
6
7
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
Decoder Generates Appropriate
Minterm based on Control Signals
C
Example Function:
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')
ECE C03 Lecture 4
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Decoder as a Logic Building Block
Enb
4:16
dec
S3 S2 S1 S0
A
B C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
F1
F2
F3
D
If active low enable, then use NAND gates!
ECE C03 Lecture 4
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Read-Only Memories
ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"
Width of row is called bit-width or wordsize
Address is input, selected word is output
+5V +5V +5V +5V
n
2 -1
Dec
i
Word Line 0011
j
Word Line 1010
0
0
n-1
Address
Bit Lines
C03 Lecture 4
Internal ECE
Organization
37
Implementing Logic with ROMs
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
A
0
0
0
0
1
1
1
1
Address
ROM
8 w ords ¥by
4 bits
A B C
address
F0
F1
F2
outputs
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F0
0
1
0
0
1
1
0
0
F1
0
1
1
0
0
0
0
1
F2
1
1
0
0
1
0
0
0
F3
0
0
0
1
1
0
1
0
Word Contents
F3
ECE C03 Lecture 4
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ROMs vs PLAs
Memory array
Not unlike a PLA
structure with a
fully decoded
AND array!
Decoder
2n word
lines
n address
lines
2n words by
m bits
m output
lines
ROM vs. PLA:
ROM approach advantageous when
(1) design time is short (no need to minimize output functions)
(2) most input combinations are needed (e.g., code converters)
(3) little sharing of product terms among output functions
ROM problem: size doubles for each additional input, can't use don't cares
PLA approach advantangeous when
(1) design tool like espresso is available
(2) there are relatively few unique minterm combinations
(3) many minterms are shared among the output functions
ECE C03 on
Lecture
PAL problem: constrained fan-ins
OR4 planes
39
Summary
•
•
•
•
•
•
Review of Combinational Logic Technologies
Programmable Logic Devices (PLA, PAL)
MOS Transistor Logic
Multiplexers/Decoders
ROM
READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4,
5.5 5.6, 5.7, 6.2
ECE C03 Lecture 4
40