Download Electronic II (ECE235b) Power Amplifiers

Electronic II (ECE235b)
Power Amplifiers
Anestis Dounavis
The University of Western Ontario
Faculty of Engineering Science
Power Amplifiers
14.1 Classification of Output stages





An amplifier receives a signal from some input source and provides a larger version of the
signal to some output device or to another amplifier stage.
The last stage (output stage) of an amplifier must provide a low output resistance so that the
amplifier can deliver the output signal to the load without loss of gain.
The final stage of the amplifier usually deals with relatively large signals, thus small-signal
models are either not applicable or must be used with care. However, the linearity of the signal
is still very important.
Large signal or power amplifiers primarily provide sufficient power to an output load to drive a
speaker or some other power device, typically greater than 1W.
The main features of a power amplifier are: 1) the circuits power efficiency, 2) the maximum
amount of power that the circuit is capable of handling, and 3) the impedance matching to the
output device.
One method to categorize amplifiers is by class. Amplifier classes represent the amount the output
signal varies over one clock cycle of operation for a full cycle of input signal. Figure 14.1 illustrates the
classification for the case of a sinusoidal input signal
Figure 14.1 Collector current waveforms for transistors operating in (a) class A, (b) class B, (c) class
AB, and (d) class C amplifier stages.
Class A:
 The output signal varies for a full 3600 of the cycle. This requires that the bias current to be
greater than the amplitude of the signal current (Figure 14.1a).
Class B:
 A class B circuits provides an output signal varying over one-half the input signal cycle (i.e.
1800 of the signal). The DC biasing point for class B is therefore 0V, with the output varying
from the bias for a half-cycle (Figure 14.1b).
 Obviously, the output is not a faithful reproduction of the input if only one half-cycle is present.
Two class B operations can be combined to provide an output of 3600 of operation.
Class AB:
 Class AB involves biasing the transistor at a nonzero DC current much smaller than the peak
current of the sine-wave signal (Figure 14.1c). The resulting conduction angle is greater than
1800 but much less than 3600.
Class C:
 The output of a class C amplifier is biased for operation at less than 1800 of the cycle. To obtain
a sinusoidal output voltage, the current is passed through a parallel LC circuit, tuned to the
frequency of the input sinusoidal (Figure 14.1d).
14.2 Class A Output Stage

Because of its low input resistance the emitter follower (common collector) is the most popular
class A output stage for BJTs. For FETs the source follower or common drain is used.
14.2.1 Transfer Characteristics
Figure 14.2 shows an emitter follower (transistor Q1) biased with a constant current source I supplied
by transistor Q2.
Figure 14.2 An emitter follower (Q1) biased with a constant current I supplied by transistor Q2.


The emitter current is: i E1  I  i L
The bias current I must be greater than the largest negative load current; otherwise, Q1 cuts off
and class A operation will no longer be maintained.
The transfer characteristic of the emitter follower is described by:
vO  v I  v BE1
If we, neglect the relatively small changes in v BE1 , the linear transfer curve shown in Figure 14.3
results
Figure 14.3 Transfer characteristic of the emitter follower in Fig. 14.2. This linear characteristic is
obtained by neglecting the change in vBE1 with iL. The maximum positive output is determined by the
saturation of Q1. In the negative direction, the limit of the linear region is determined either by Q1
turning off or by Q2 saturating, depending on the values of I and RL.

The upper limit of the linear region is determined:
vO max  VCC  VCE1sat
 The lower limit occurs when either Q1 is turns off
vO min   IRL
or by saturating Q2.
vO min  VCC  VCE 2 sat
The saturation of Q2 occurs when
| VCC  VCE 2 sat |
I
RL
14.2.3. Power Dissipation
Next, assume that a sinusoidal waveform signal input for the circuit in Figure 14.2.
 Neglecting VCEsat , if the current is properly selected, the output voltage can swing from  VCC to
VCC .
 The waveforms vO , vCE1  VCC v O and iC1 are shown in Figure 14.4. The waveform of Figure
14.4c) assumes that the bias current I is selected to allow maximum negative load current of
VCC / R L .
Figure 14.4 Maximum signal waveforms in the class A output stage of Fig. 14.2 under the condition I
= VCC /RL or, equivalently, RL = VCC /I.


The instantaneous power dissipated in Q1 is: p D1  vCE1iC1 (Figure 14.4d).
The maximum instantaneous power dissipated in Q1 is:
Quiescent power dissipation = P ( DC )  VCC I

Note: the emitter-follower transistor dissipates the largest amount of power when vO  0 . Thus
if no input signal, the transistor Q1 must be able to withstand a continuous power dissipation of
P ( DC )  VCC I
The power dissipation of Q1 depends on the load value RL.
 When R L   then iC1  I , if vO  VCC , then vCE1  2VCC and the maximum power is
p D1  2VCC I .
 When R L  0 . This can result in a large current through Q1, and if conditions persist can cause
Q1 to burn up.
Power dissipation of Q2: maximum power dissipation when vO  VCC p D 2  2VCC I
14.2.4 Power-Conversion Efficiency
The power-conversion efficiency of an output stage is defined as
Load power ( PL )

Supply power ( PS )
Assuming that the output voltage is sinusoidal with the peak value of VˆO , the average power at the load
is
2
2
(Vrms ) 2 1 (V peak )
1 VˆO


RL
2 RL
2 RL
The total average supply power (negative and positive supply; does not include transistor Q3 and
resistor R) is
PS  2VCC I
Thus the power-conversion efficiency can be expressed as:
2
1 VˆO
1  Vˆ  Vˆ 

  O  O 
4 IRL VCC 4  IR L  VCC 
Since VˆO  VCC and VˆO  IR L , the maximum efficiency is when VˆO  VCC  IRL . Thus the maximum
efficiency attainable is 25%.
PL 
Exercise 14.4:
For the emitter follower of Figure 14.2, let VCC  10V , I=100mA, and R L  100 . If the output voltage
is 8-V-peak sinusoid find
1. Power delivered to the load
2. Average power drawn from the supplies
3. the power conversion efficiency
Example
Calculate the input power, output power and efficiency of the amplifier circuit shown below for an
input voltage that results in a base current of 10mA peak.
14.3 Class B Output Stage
Figure 14.5 shows a class B output stage. This configuration consists of a complementary pair of
transistors (an npn and a pnp) connected in such a way that both cannot conduct simultaneously.
Figure 14.5 A class B output stage.
Operation
 When the input voltage v I is zero, both transistors are cut off and the output voltage vO is zero.
 When v I goes positive and exceeds about 0.5V, QN conducts and operates as an emitter
follower. The output voltage is vO  v I  v BE N . The transistor QP is off.
 If the input is negative, more than 0.5 V, QP conducts and acts as an emitter follower. The
output voltage is vO  v I  v BEP . The transistor QN is off
The transfer characteristic of the class B stage is shown in Figure 14.6. The region in which both
transistors are off are referred to as the dead band. This results in crossover distortion as illustrated in
Figure 14.7.
Figure 14.6 Transfer characteristic for the class B output stage in Fig. 14.5.
Figure 14.7 Illustrating how the dead band in the class B transfer characteristic results in crossover
distortion.
14.3.3 Power-Conversion Efficiency
To calculate the power-conversion efficiency of the class B stage, we neglect the crossover distortion
and consider the case of an output sinusoidal of peak amplitude VˆO .
2
2
(Vrms ) 2 1 (V peak )
1 VˆO
PL 


RL
2 RL
2 RL
The current drawn from each supply will consist of half-sine waves of peak amplitude Vˆ / R .
O
 Thus the average current drawn from each of the 2 power supplies VˆO /(R L )
 Thus the power from each supply is
Vˆ
PS   PS   VCC I  VCC O
R L
 The total power from the supplies will be
2Vˆ
PS  O VCC
 RL
The efficiency becomes
 1 VˆO2   2VˆO
  VˆO
 

  
V
CC
  R
 4V
2
R
L 
CC

 L

ˆ
The maximum efficiency is achieved when VO  VCC  VCEsat  VCC . Thus

 max   78.5%
4
L
14.3.4 Power Dissipation
Under quiescent conditions ( v I  0 ), the quiescent power dissipation of the class B is zero.
When an input signal is applied, the average dissipated in the class B stage is given by
2Vˆ
1 VˆO2
PD  PS  PL  O VCC 
R L
2 RL
1
 From symmetry QN and QP must be capable of dissipating PD watts.
2
P
The value of D depends on the amplitude of the output signal, thus to find the maximum value of PD ,
the expression is differentiated w.r.t. Vˆ and the result is equated to zero to yield:


O
VˆO
PD max

2
VCC

Substituting this value into PD yields
2
PD max 
2VCC
 2RL
Thus
2
PDN max  PDQ max 
VCC
 2 RL
At this point, the efficiency can be evaluated to be:
 VˆO
 (2VCC /  )


 1 / 2  50%
4 VCC 4 VCC
Figure 14.8 plots power dissipation versus the amplitude of the output voltage.
Figure 14.8 Power dissipation of the class B output stage versus amplitude of the output sinusoid.


Note that increasing VˆO beyond 2VCC /  decreases the power dissipation in the class B stage
while increasing the load power.
The price is an increase in nonlinear distortion due to the dead band region. The distortion can
be reduced by using negative feedback.
Exercise 14.5
For the class B output stage Figure 14.5, let VCC  6V and R L  4 . If the output is a sinusoid with
4.5V peak amplitude, find
1. The output power
2. The average power drawn from each supply
3. The power efficiency obtained at this stage.
4. The peak currents supplied by v I , assuming  N   P  50 .
5. The maximum power that each transistor must be capable of dissipating safely.
14.4 Class AB Output Stage
The crossover distortion can be virtually eliminated by biasing the transistors at a small nonzero
current. This gives a class AB output stage as shown in Figure 14.11.
Figure 14.11 Class AB output stage. A bias voltage VBB is applied between the bases of QN and QP,
giving rise to a bias current IQ given by Eq. (14.23). Thus, for small vI, both transistors conduct and
crossover distortion is almost completely eliminated.

For v I  0 , vO  0 , and a voltage V BB / 2 and both transistors are on. Assuming matched
devices
i N  i P  I Q  I S eVBB /( 2VT )
The value of V BB is selected to give required quiescent current I Q .

When v I is positive by a certain amount, the transistor QN is in the active region and the output
voltage vO becomes positive at an almost equal value:
vO  V I  V BB / 2  v BEN
The positive voltage vO causes current to flow through R L where
iL  i N  iP
Thus the current i N is much greater than i P due to the positive applied input voltage v I

The relationship of the currents can be derived as:
v BEN  v EBP  VBB
VT ln
IQ
iN
i
 VT ln P  2VT ln
IS
IS
IS
iN iP  I Q
2
Thus as i N increases, i P decreases by the same ratio

2
Combining i L  i N  i P with i N i P  I Q yields the following relationship between i N and i L
2
i N  i N i L  I Q2  0
From this analysis, for positive output voltage, the load current is supplied by QN. As the output
voltage increases, the current QP can be ignored altogether. For negative input voltage the opposite
occurs. Figure 14.12 shows the transfer characteristic of the class AB.
Figure 14.12 Transfer characteristic of the class AB stage in Fig. 14.11.
Power Dissipation



The power relationships of class AB stage are almost identical to those derived for the class B
circuit.
The only difference is that under quiescent conditions ( v I  0 ), the quiescent power dissipation
of the class AB is VCC I Q per transistor. Thus the total quiescent power dissipation is 2VCC I Q .
The quiescent power dissipation is relatively small since I Q is usually much smaller than the
peak load current.
We can add the quiescent power dissipation to its maximum power dissipation with an input
signal applied to obtain the total power dissipation that the transistor must be able to handle
safely.
14.4.2 Output Resistance
The output resistance of Figure 14.4.2 is
Figure 14.13 Determining the small-signal output resistance of the class AB circuit of Fig. 14.11.
Rout  reN || reP
The emitter resistances are given by:
VT
iN
reP 
Rout 
VT VT
VT
||

iN iP iP  iN
reN 
VT
iP
Thus


When i N increases, i P decreases and vice versa, the output resistance remains approximately
constant in the region when v I  0 . This is the reason for the virtual absence of crossover
distortion.
At larger load currents, either i N or i P becomes significant. This causes the output resistance to
decrease.
14.5 Biasing the Class AB Circuit
14.5.1 Basing Using Diodes
One way to bias a class AB circuit is to use diodes as shown in Figure 14.14. The bias voltage is
generated by passing a constant current I BIAS through a pair of diodes, or diode connected transistors.
Figure 14.14 A class AB output stage utilizing diodes for biasing. If the junction area of the output
devices, QN and QP, is n times that of the biasing devices D1 and D2, and a quiescent current IQ =
nIBIAS flows in the output devices.


In circuits that supply large amounts of power, the output transistors are large geometry devices.
The biasing diodes, however, need not be large devices thus the quiescent current I Q established
by QN and QP will be
I Q  nI BIAS
when n is the ration of the emitter-junction area of the output devices to the junction area of the
biasing diodes. (The saturation current I S of the output transistors is n times that of the diodes)
Disadvantages of using diodes to bias the class AB circuit
 When the circuit in figure 14.14 provides current to the load, the base current of QN increases
from I Q /  N to approximately i L /  N .
 Thus the current I BIAS must be greater than the maximum anticipated base current source I BIAS .
(This sets a lower limit for I BIAS )
 Note I Q  nI BIAS , and since I Q is much smaller than the peak load current (<10%), we can not
make n a large value. Thus the disadvantage of the diode biasing scheme is that we can not
make the diodes much smaller than the output devices.
Advantages of using diodes to bias the class AB circuit
 One advance of the diode biasing arrangement is that it can provide thermal stabilization of the
quiescent current at the output stage.
 As temperature increases, this decreases the voltage between the base and the emitter V BE
(approximately -2mV/oC) if the collector current is held constant.
 Thus if V BE is held constant and the temperature increases, the collector current increases.



The increase in collector current increases the power dissipation, which in turn further increases
the collector current.
This positive feedback mechanism is called thermal runaway.
The diode biasing configuration prevents thermal runaway under quiescent conditions. If the
diodes are in close thermal contact with the output transistors their temperature will increase by
the same amount as the out transistors. Thus V BB will decrease by the same rate as V BEN  V BEP
14.5.2. Biasing Using the VBE Multiplier
An alternative biasing arrangement is shown in Figure 14.15.
Figure 14.15 A class AB output stage utilizing a VBE multiplier for biasing.
The circuit of Figure 14.15 operates as:
 Neglecting the base current of Q1, then
V BE1  I R R1
VBB  I R ( R1  R2 )  V BE1 (1 
R2
)
R1
R2
) and if referred to as the V BE multiplier.
R1

Thus this circuit simply multiplies V BE1 by (1 

The circuit designer picks the appropriate multiplication factor to establish the required V BB to
yield the desired quiescent current I Q . In discrete circuit design, a potentiometer can be used to
control the accuracy of the ratio of 2 resistances as shown in Figure 14.16.
V BE1 is determined by the portion of I BIAS :
I 
VBE 1  VT ln  C1 
I C1  I BIAS  I R
 I S1 

Figure 14.16 A discrete-circuit class AB output stage with a potentiometer used in the VBE multiplier.
The potentiometer is adjusted to yield the desired value of quiescent current in QN and QP.
Example 1
For the circuit shown, find
1. The input power, output power, and power handled by each output transistor and the circuit
efficiency for an output voltage of 12V rms.
2. Calculate the maximum input power, maximum output power, output voltage for maximum
power operation and the power dissipated by the output transistor at this voltage.
3. Determine the maximum power dissipated by the output transistors and the output voltage at
which it occurs.
14.6 Power BTJs
Transistors that are required to conduct currents in the ampere range and withstand power dissipation in
the watts or tens-of-watts differ in physical structure, packaging and specification from the small-signal
transistors considered in earlier.
Junction Temperature
 Power transistors dissipate large amounts of power in their collector-base junction.
 The dissipated power in converted into heat, which raises the junction temperature.
 The junction temperature TJ must not exceed a specified maximum TJ max ; otherwise the
transistor could suffer permanent damage.
 For silicon devices TJ max ranges between 1500C to 2000C.
Thermal Resistance
 A transistor operating in free air, that dissipates PD watts, the temperature rise of the junction
relative to the surrounding ambience can be expressed as
TJ  TA   JA PD
where  JA is the thermal resistance between the junction and the ambience, having the units of
degrees Celsius per watt.
 To dissipate large amounts of power without raising the junction temperature above TJ max , it is
desirable for the thermal resistance to be  JA to be as small as possible. For operation in free air
 JA depends primarily on the type of case in which the transistor is packaged.  JA is usually
specified on the transistor data sheet.
 TJ  T A   JA PD is analogous to Ohm’s law which describes the electrical conduction process.
In this analogy, power dissipation corresponds to current, the temperature difference
corresponds to voltage difference and thermal resistance corresponds to electrical resistance.
Thus the thermal conduction equations can be represented by the electric circuit shown in
Figure 14.17
Figure 14.17 Electrical equivalent circuit of the thermal-conduction process; TJ – TA = PDqJA.
Power Dissipation Versus Temperature
The transistor manufacturer usually specifies the following parameters:
1. The maximum junction temperature TJ max .
2. The maximum power dissipation at a particular ambient temperature T A0 (usually, 25oC).
3. The thermal resistance  JA .
4. In addition a graph such as Figure 14.18 is provided.
Figure 14.18 Maximum allowable power dissipation versus ambient temperature for a BJT operated in
free air. This is known as a “power-derating” curve.
The graph simply states that for operation at ambient temperatures below TA0 , the device can safely
dissipate the rated value of PD 0 watts.
 However, if the device is to be operated at higher ambient temperatures, the maximum
allowable power dissipation must be derated (decreased) according to the straight line shown in
Figure 14.18.
 Using TJ  T A   JA PD and Figure 14.18 yields:
T  T A0
 JA  J
PD
The thermal resistance  JA is the inverse of the slope of the power-derated straight line.
 The maximum power dissipation PD max at a given ambient temperature can be obtained by
T
 T A0
PD max  J max
 JA
The BJT Safe Operating Area
Power-transistor manufactures usually provide a plot of the boundary of the safe operating area (SOA)
in the iC  vCE plane (Figure 14.23).
Figure 14.23 Safe operating area (SOA) of a BJT.
The following paragraphs numbers correspond to the boundaries on the sketch.
1. I C max is the allowable maximum collector current. Exceeding this current value can result in
melting the wires that bond the device to the package.
2. The maximum power dissipation hyperbola can be used to determine PD max  vCE iC (at TC 0 ).
For temperatures TC  TC 0 , the power-derating curves should be used to obtain the applicable
PD max .
3. The second breakdown region occurs because the current flow across the emitter-base junction
is not uniform. The current density is greatest near the periphery of the junction. This gives rise
to an increase in localized power dissipation and hence temperature rises at locations called hot
spots.
4. BVCEO is the collector-emitter breakdown voltage. The instantaneous value of vCE should never
exceed BVCEO , otherwise, avalanche breakdown of the collector-base junction may occur.
Example 2
Determine what the maximum dissipation will be allowed for an 80W silicon transistor (rated at 250C)
if derating is required above 250C by a derating factor of 0.5 W/0C at a case temperature of 1250C.
14.7 Variations on the Class AB Configuration
14.7.1 Use of Input Emitter Followers
Figure 14.24 shows a class AB circuit.
Figure 14.24 A class AB output stage with an input buffer. In addition to providing a high input
resistance, the buffer transistors Q1 and Q2 bias the output transistors Q3 and Q4.

The class AB circuit is biased using transistors Q1 and Q2, which act as a unity gain buffer
amplifier.
 All 4 transistors are usually matched, thus the quiescent current (i.e. v I  0 , R L   ) in Q3 and
Q4 is equal to that in Q1 and Q2.
 Resistors R3 and R4 are usually very small and are included to compensate for possible
mismatches between Q3 and Q4 and to guard against the possibility of thermal runaway due to
temperature differences between the input and output stages.
 Note that an increase in current in Q3 causes an increase in voltage drop in R3 and a
corresponding decrease in VBE 3 , thus guarding against thermal runaway.
Note that the circuit of Figure 14.24 requires high-quality pnp transistors and is not suitable for
implementation in conventional monolithic IC technology. However, circuit can be implemented in
hybrid thick-film technology.
14.7.2 Use of compound devices
The Darlington circuits shown in Figure 14.25 and Figure 14.26 are often used to increase the current
gain of the output stage transistor and thus reduce the required base current.
Figure 14.25 The Darlington configuration.
Figure 14.26 The compound-pnp configuration.


The Darlington circuit (Figure 14.25) is equivalent to having npn transistor having    1  2
and almost twice the value of V BE .
The Darlington circuit for the pnp (Figure 14.26) is equivalent to having pnp transistor having
  1  2 and almost twice the value of V BE .
The application of the Darlington circuit to a class AB circuit is shown in Figure 14.27. The circuit of
Figure 14.27 is similar to Figure 14.15.
 Note the Darlington configuration adds more V BE drop and the V BE multiplier is required to
provide a bias voltage of about 2V.
Figure 14.27 A class AB output stage utilizing a Darlington npn and a compound pnp. Biasing is
obtained using a VBE multiplier.
14.7.3 Short-Circuit Protection
Figure 14.28 shows a class AB equipped with protection against the effect of short-circuiting the output
while the stage is sourcing current.
Figure 14.28 A class AB output stage with short-circuit protection. The protection circuit shown
operates in the event of an output short circuit while vO is positive.




In the event of a short circuit, the large current that flows through Q1 will creat a voltage drop
across R E1 of sufficient value to turn Q5 on.
The collector of Q5 will conduct most of the current IBIAS, thus the base current of Q1 will be
significantly reduced causing Q1 to operate at a safe level.
The disadvantage of this configuration is that under normal operation about 0.5V drop appear
across each R E . This means that the output voltage swing will be reduced by that much.
Additional benefit of this circuit is that it protects against thermal runaway.