Download Programming

Assembly and Other Programming
Languages
z
Programming
A.
B.
C.
D.
E.
F.
G.
H.
Machine language: binary encoding of
instructions that are executed by a CPU
z
z
Assembly and Other Programming Lang.
Source Code, Object Code, and the Assembler
C Language for Microcontrollers
Fetch/Execute Operations of CPU
The Instruction Set and Addressing Modes
68HC11 Instruction Set
Microcontroller Arithmetic and the CCR
Program Flow Control Using Looping &
Branching
z
each CPU has its own machine language
Ex: %10000110; %01011010
Assembly language: machine instructions are
represented into a mnemonic form
z
z
mnemonic form is then converted into actual
processor instructions and associated data
Ex:
LDAA #$5A
10000110
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01011010
1
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Assembly and Other Programming
Languages
z
Assembly and Other Programming
Languages
Disadvantages of AL
z
z
z
z
z
require knowledge of the processor architecture
and instruction set
many instructions are required to achieve small
tasks
source programs tend to be large and difficult to
follow
programs are machine dependent => requiring
complete rewriting if the hardware is changed
High level languages
z
z
z
z
z
z
3
human like languages
Ex: Basic, Pascal, FORTRAN, Ada, Cobol, C, Java
C: most common high-level language for
microcontroller development
Advantages
z
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portable
the source program is translated into machine code
for each type of CPU
What is different is the translator not the program
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1
Source Code, Object Code, and the
Assembler
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Programming
z
z
A.
B.
C.
D.
E.
F.
G.
H.
Assembly and Other Programming Lang.
Source Code, Object Code, and the Assembler
C Language for Microcontrollers
Fetch/Execute Operations of CPU
The Instruction Set and Addressing Modes
68HC11 Instruction Set
Microcontroller Arithmetic and the CCR
Program Flow Control Using Looping &
Branching
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z
z
Machine language
Assembly language
Examples
Manual assembly
The simulator
5
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Source Code, Object Code, and the
Assembler
z
z
z
z
Machine Language
Source code
z
Represents original program before it is translated
Stored as a file
Assembly program applications are more efficient
than one written in a high level languages
Efficiency
z
z
Machine language
can directly control
the microcontroller’s
resources
z
Ex: LDAA #$5A
Code must be
stored in memory
z
refers to code size, execution size, energy
consumption
z
z
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7
$E000: $86
$E001: $5A
Fetch/Execute Cycle
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2
Machine Language
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z
Instruction: opcode; operand
Opcode specifies the type of operation
z
z
z
Assembly Language
z
68HC11 uses 1-byte and 2-bytes opcodes
2-byte opcodes are composed of a prebyte
followed by the real opcode
z
Mnemonic that
specifies the start
address of a program
Operand tells the CPU what data to operate on
z
Assembly language programs use mnemonics
and are typed using a text editor
Machine code must be stored in memory
ORG $E000
LDAA # $ 5A
An instruction may have 0, 1, 2 or 3 operand bytes
Mnemonic
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Assembly Language
Assembler
10
Why do we need a linker?
z
z
Assembly
Language
Development
System
z
z
11
translate source code directly into machine code
Disassembler
z
Hex Code
one writes the source code in smaller sections
the linker helps to develop large applications
Line assemblers
z
Linker
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Operand
Assembly Language
Assembly
Source Code
Relocatable
Object Format
Hex
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Text Editor
Immediate
translating program that reverses the machine code
into the assembly source code
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3
Examples
Coolant
Temperature
Examples
PROGRAM:
a. read input
b. subtract an offset
c. store the result
µ
controller
The labels are assigned using assembler directives:
COOLANT_TEMP
CT_OFFSET
STORE_TEMP
* Assembly language program
ORG $E000
LDAA $1031 or
SUBA #$20 or
STAA $D004 or
LDAA COOLANT_TEMP
SUBA #CT_OFFSET
STAA STORE_TEMP
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Manual Assembly
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The Simulator
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Using the manual of the instruction set summary
we can convert source code into hex code
address
LDAA 1031
SUBA #20
STAA D004
EQU $1031
EQU $20
EQU $D004
z
E000: B6 10 31
E003: 80 20
E005: B7 D0 04
A microcontroller simulator is a software tool
that permits users to simulate the operation of
a microcontroller
The book contains the demo version of the
THRSim 11
By convention machine code is always hex
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4
C Language for Microcontrollers
z
z
Programming
z
z
A.
B.
C.
D.
E.
F.
G.
H.
Assembly and Other Programming Lang.
Source Code, Object Code, and the Assembler
C Language for Microcontrollers
Fetch/Execute Operations of CPU
The Instruction Set and Addressing Modes
68HC11 Instruction Set
Microcontroller Arithmetic and the CCR
Program Flow Control Using Looping &
Branching
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High level languages
compiled languages
interpreted
Why C is popular?
z
z
combines the best of
both, the high-level
language and the
assembly language
has features to allow
direct control of I/O which
is very important for
microcontroller
applications
Design Program
Write the C source code
Compile the program
to produce object code
Link the object code
C Library
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C Language for Microcontrollers
z
z
Most C compilers for microcontrollers follow
the early standard defined by Kernigham and
Ritchie in 1978
Normally the assembly language created by
the C compiler is less efficient however, using
C the development of large applications is
easier
Programming
A.
B.
C.
D.
E.
F.
G.
H.
Assembly and Other Programming Lang.
Source Code, Object Code, and the Assembler
C Language for Microcontrollers
Fetch/Execute Operations of CPU
The Instruction Set and Addressing Modes
68HC11 Instruction Set
Microcontroller Arithmetic and the CCR
Program Flow Control Using Looping &
Branching
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19
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Fetch/Execute
Operation of CPU
Clear Accumulator A
Load Accumulator A
Fetch/Execute
Operation of CPU
Control Sequencer
Instruction decoder
ALU
CPU operation
Executing the first
instruction CLRA
CLRA
LDAA #$5C
E000: 4F
E001: 86 5C
CPU operations
Fetching CLRA
AR: address reg.
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Fetch/Execute
Operation of CPU
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Fetch/Execute
Operation of CPU
CPU operation
Fetching the second
instruction operand
($5C) and executing
the instruction
CPU Operation
Fetching the second
instruction opcode LDAA#
Note: PC increments
to point to the next
byte to be fetched
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The Instruction Set and Addressing
Modes
z
z
Programming
z
z
A.
B.
C.
D.
E.
F.
G.
H.
Assembly and Other Programming Lang.
Source Code, Object Code, and the Assembler
C Language for Microcontrollers
Fetch/Execute Operations of CPU
The Instruction Set and Addressing Modes
68HC11 Instruction Set
Microcontroller Arithmetic and the CCR
Program Flow Control Using Looping &
Branching
z
z
z
z
z
z
z
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Instruction set references
Types of instructions
Addressing modes
The prebyte
Inherent addressing mode
Listing and execution conventions
Stopping a program
Immediate addressing mode
Direct and extended addressing modes
Indexed addressing mode
Memory dump convention
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Instruction Set References
Instruction
Set
References
Programming model
of the 68HC11
The instruction set summary can give enough
information for using the assembly language
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Instruction Set References
Types of Instructions
Instruction set summary. Operand Notations
dd = 8-bit direct address ($0000-$00FF)
(High byte assumed to be $00)
ff = 8-bit positive offset $00 (0) to $FF (256)
(Is added to the index)
hh = high order byte of 16-bit extended address
ii = one byte of immediate data
jj = high order byte of 16-bit immediate data
kk = low order byte of 16-bit immediate data
ll = low order byte of 16-bit extended address
mm = 8-bit bit mask (Set bits to be affected)
rr = signed relative offset $80(-128) to $7F(+128)
(Offset relative to the address following the
machine code offset byte
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Addressing Modes
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Prebyte
Inherent
Immediate
Extended
Direct
Indexed
Relative
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z
z
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Data handling
Arithmetic
Logic
Data test
Jump and branch
Conditional code
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Opcodes based on the earlier 6801
microcontroller have a single byte
New instructions + any instruction dealing with
index register Y have 2-byte opcodes
A few hex numbers were reserved for the first
opcode to specify that the following byte is also
part of the opcode
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8
Inherent Addressing Mode
Inherent addressing,
the opcode does not require
an operand
Inherent
Addressing
Mode
Operations
Initial condition
0→A
B+1 → B
Y → D, D → Y
Y-1 → Y
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Listing and Executing Conventions
$E000
;define start address
4F
CLRA ;clears ACCA
5C
INCB ;increment ACCB
18 8F XGDY ;swap ACCD with IY
18 09 DEY ;decrement IY
PC
ACCA ACCB IY
Operation
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STOP: stop processing
z
z
z
Program trace
z
E000
E001
E002
E004
E006
6A
00
00
1A
1A
80
80
81
47
47
1A47
1A47
1A47
0081
0080
Initial cond.
0→A
B+1 → B
Y → D, D → Y
Y-1 → Y
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Stopping a Program
Listing
ORG
E000
E001
E002
E004
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Opcode: CF
stops internal clocks, puts
the processor in the
standby mode
recovery from STOP may
be accomplished by
RESET^ or an interrupt
there are potential
problems with the STOP
instruction (M68HC11)
z insert a NOP before
STOP
z
BRA *
z
z
z
z
z
z
z
BRA (rel)
Branch always
Opcode: 20
Operation: PC ← (PC) +
$002 + rr
Operands: rr
Note: rr represents signed
relative offset
The assembler obtains
the relative address, Rel,
from the absolute address
and the current value of
the location counter
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Immediate Addressing Mode
Immediate Addressing Mode
Immediate addressing
example
# prefix indicate immediate
Program example containing instructions that
use immediate addressing
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Extended Addressing Mode
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Extended Addressing Mode
STAA $6D00 ; two-byte operand for extended mode
z
no # prefix
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In the extended addressing mode, the effective
address (EA) of the instruction appears
explicitly in the two bytes following the opcode
The length of the most instructions using
extended mode is 3 bytes
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Direct Addressing Mode
Direct Addressing Mode
LDAA $1B ; one-byte operand that is an address
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z
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The least significant
byte of the effective
address (EA) of the
instruction appears in
the byte following the
opcode
The high-order byte of
the EA is assumed to be
$00
Direct page is defined
by the EA limits: $0000$00FF
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z
z
Advantages
the execution time is
reduced by one cycle
In the M68HC11 MCU
the software can
configure the memory
map so that internal
RAM, and/or internal
registers or external
memory space can
occupy these addresses
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Direct and Extended Addressing
Modes
Direct and Extended Addressing Modes
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Accessing
input/output ports
z
First reference to CAT is a forward reference and the
assembler selected the extended mode
Second reference, the assembler knows the symbol value
⇒ direct mode
Last reference, extended mode since CLR has no direct mode
Some assemblers allow the direct or extended addressing
modes to be forced by using < or > before the operand
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z
z
Each bit of an I/O
port corresponds to
an external pin of the
I/O port
Two of 68HC11 ports
are port B (output)
and port C (input)
The addresses of
their corresponding
registers are $1004
and $1003
LDAA #$A5 ;load data to
be outputted
STAA $1004 ;send it to
port B
LDAA $1003 ;read data
from port C
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Indexed Addressing Mode
z
z
In the index addressing
mode, either index
register X or Y is used in
calculating the effective
address (EA)
EA is variable and
depends on the content
of index registers X or Y
and a fixed, 8-bit,
unsigned offset
contained in the
instruction
z
z
Dynamic single-byte
offsets are facilitated by
the use of the add
accumulator B to index
register X (ABX) instr.
More complex address
calculations can be
obtained by the use of
instructions XGDX and
XGDY
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Indexed
Addressing
Mode
Machine
Opcode
LDAA $56,X
Access on-chip
Index Reg
X
registers:
initialize the index
register to the starting
address of the
register block and use
an 8-bit offset
Operand, offset
Memory
Data
Address
Accumulator
A
45
Index Addressing Mode
Source
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Index Addressing Mode
For look-up table applications
ORG $E000 ;start address
OPERATIONS
LDAA $00,X ;load with indexed mode
ADDA $01,X ;add with indexed mode
STAA $20,Y ;store with indexed mode
ABY
;an inherent mode
*
;instruction to modify IY
INY
;another one which
*
;increments IY
STAA $30,Y ;again, store using
*
;indexed mode
BRA *
;stop program
(X+0) → A
A+(X+1) → A
A → (Y+20)
B+Y → Y
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ORG $E000
;address $30 contains the data from the sensor
LDAB $30
;get stored differential
;pressure signal
LDX #$B600 ;point to square root table
ABX
;look up its square root
LDAA $00,X ;and load it to find flow rate
F=K√(h)
Y+1 → Y
Microcontroller reads a signal from a sensor and
stores it at address $30
Block of memory starting at $B600 contains
the square root of all single-byte numbers
A → (Y+30)
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Indexed
Addressing
Mode
Relative Addressing Mode
z
Table[0x00]
Table[0x01]
Table[0x02]
Table[0x03]
0x00
0x10
0x17
0x1C
Table[0xd0]
0xed
Table[0xfe]
Table[0xff]
0xff
0xff
z
z
z
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Relative Addressing Mode
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Memory Dump Conventions
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z
z
Assembly language statements
Examples of relative addressing mode
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Relative addressing mode is used only for
branch instructions
Usually the branch instructions generate two
machine-code bytes: one for opcode and one
for the relative offset
The offset byte is signed 2s-complement with
a range for -128 to +127
A branch always (BRA) instruction with an
offset of $FE will result in an infinite loop back
to itself
A memory dump is a print of the content of the
memory
A dump consists of one or more rows of hex
numbers
The contents (data) of memory are the 16
bytes that follow the address
0020 xx xx xx xx xx xx xx 54 – 68 65 20 44 75 6D 70 2E
0030 0D 0A xx xx xx xx xx xx - xx xx xx xx xx xx xx xx
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M68HC12 Versus M68HC11
Similarities
z
Programming
A.
B.
C.
D.
E.
F.
G.
H.
z
Assembly and Other Programming Lang.
Source Code, Object Code, and the Assembler
C Language for Microcontrollers
Fetch/Execute Operations of CPU
The Instruction Set and Addressing Modes
68HC11 Instruction Set
Microcontroller Arithmetic and the CCR
Program Flow Control Using Looping &
Branching
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The programmer’s model and interrupt
stacking order for the CPU12 are identical to
that of M68HC11
All source code for the M68HC11 is accepted
by CPU12 with no modifications
Most M68HC11 instructions even assemble to
the same object code on the CPU12
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M68HC12 Versus M68HC11
M68HC12 Versus M68HC11
Improvements
Improvements
z
z
z
z
Most obvious improvement is that the CPU12
is a 16-bit processor with an ALU that is 20
bits wide for some operations
All data busses in the M68HC12 are 16-bits
External bus interface is normally 16-bits
although a narrow 8-bit option can be selected
There is an instruction queue (similar to a
pipeline) that caches program information so
that at least 2 more bytes of object code are
visible to CPU at the start of execution
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z
z
Due to the queue feature, many instructions
can execute in one cycle with no delay for
fetching additional program information
The indexed addressing mode has been
enhanced
z
z
z
54
in M68HC11 Y-relative indexed instructions had an
extra prebyte. As a result the instructions have an
extra byte and an extra clock cycle
In CPU12, all indexed instructions have an opcode
(a postbyte, and 0, 1, 2 extension bytes
Also there are new instruction and basically
the old set was enhanced
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14
M68HC12
z
68HC11 Instruction Set
CPU12 programming reference:
z
z
Todd D. Morton, “Embedded Microcontrollers,”
Prentice Hall, 2001 (Chapters 4 & 5).
z
z
z
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Most of these
instructions use two
operands
z
z
one operand is either an
accumulator or and index
register
whereas, the second
operand is usually
obtained from memory
z
Subgroups
z
z
z
z
z
z
Function
Clear Mem Byte
Clear Accum A
Clear Accum B
Load Accum A
Load Accum B
Load D Accum
Pull A from Stack
Pull B from Stack
Push A onto Stack
Push B onto Stack
loads, stores and
transfers
arithmetic operations
multiply and divide
logical operations
data testing and bit
manipulation
shifts and rotates
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Loads, Stores, and Transfers
Accumulator and Memory Instructions
z
Accumulator and memory instructions
Stack and index register instructions
Condition code register instructions
Program control instructions
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Mnemonic
CLR
CLRA
CLRB
LDAA
LDAB
LDD
PULA
PULB
PSHA
PSHB
IMM DIR EXT IX IY INH
*
* *
*
*
*
*
*
* *
*
*
*
* *
*
*
*
* *
*
*
*
*
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Arithmetic Operations
Loads, Stores, and Transfers
Function
Store Acc A
Store Acc B
Store D Acc
Transfer A to B
Transfer A to CCR
Transfer B to A
Transfer CCR to A
Exchange D with X
Exchange D with Y
Mnemonic
STAA
STAB
STD
TAB
TAP
TBA
TPA
XGDX
EGDY
IMM
*
*
*
DIR
*
*
*
EXT
*
*
*
IX
*
*
*
Function
Add Acc
Add Acc B to X
Add Acc B to Y
Add with Carry to A
Add with Carry to B
Add Memory to A
Add Memory to B
Add Mem to D (16b)
Compare A to B
Compare A to Mem
Compare B to Mem
Compare D to Mem
Decimal Adjust A
Decrement Mem Byte
Decrement Acc A
IY INH
*
*
*
*
*
*
*
*
*
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Arithmetic Operations
Function
Decrement Acc B
Increment Mem Byte
Increment Acc A
Increment Acc B
Twos Compl Mem Byte
Twos Compl Acc A
Twos Compl Acc B
Subtract w Carry from A
Subtract w Carry from B
Subtract Mem from A
Subtract Mem from B
Subtract Mem from D
Test for Zero or Minus
Test for Zero or Minus A
Test for Zero or Minus B
Mnemonic
DECB
INC
INCA
INCB
NEG
NEGA
NEGB
SBCA
SBCB
SUBA
SUBB
SUBD
TST
TSTA
TSTB
IMM DIR EXT IX IY INH
*
*
*
*
*
*
* *
*
*
*
* *
*
*
*
* *
*
*
*
* *
*
*
*
* *
*
*
*
*
* *
*
*
*
* *
*
*
*
* *
*
*
* *
*
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Arithmetic Operations
IMM DIR EXT IX IY INH
*
*
* *
*
*
*
* *
*
*
*
*
*
* *
*
*
*
* *
*
*
*
* *
*
*
*
* *
*
*
*
* *
*
* *
*
*
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Mnemonic
ABA
ABX
ABY
ADCA
ADCB
ADDA
ADDB
ADDD
CBA
CMPA
CMPB
CPD
DAA
DEC
DECA
z
z
Example
Add the following
numbers: $00CC+
z
z
$3276
$3342
Memory data:
0000: 00
0001: CC
0002: 32
0003: 76
0004: xx
0005: xx
63
LDAA
ADDA
STAA
LDAA
ADCA
STAA
68HC11 can add 2
bytes or 2 double bytes
The following is the
single byte addition
program
$01 ; load CC to A
$03 ; add A to 76
$05 ; store result
$00 ; load 00 to A
$02 ; add w carry A to 32
$04 ;store the result
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
64
16
Multiply and Divide
Logical Operations
Function
Mnemonic INH
Multiply
(AxB=>D)
MUL
X
Fractional Divide
(D/X => X; r=>D
FDIV
X
Integer Divide
(D/X => X; r=>D)
IDIV
X
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
Function
AND A with Memory
AND B with Memory
Bit(s) Test A with Mem
Bit(s) Test B with Mem
Ones Comp Mem Byte
Ones Complement A
Ones Complement B
OR A with Mem (excl)
OR B with Mem (excl)
OR A with Mem (incl)
OR B with Mem (incl)
65
Logic Operations
z
LDD $06 ; loads 9D to A and 9C to B
ANDA #$A5 ;ands A with A5
ORAB #$A5 ; ors B with A5
EORB $08 ; xors B with mem(08)
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
IMM
*
*
*
*
DIR
*
*
*
*
EXT
*
*
*
*
*
IX
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
IY INH
*
*
*
*
*
*
*
*
*
*
*
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
66
Data Testing and Bit Manipulation
Perform Boolean operations AND, OR, and
EXCLUSIVE OR for each bit in a byte
0000: xx xx ...
0006: 9D
0007: 9C
0008: A5
0009: xx xx ...
Mnemonic
ANDA
ANDB
BITA
BITB
COM
COMA
COMB
EORA
EORB
ORAA
ORAB
67
Function
Bit(s) Test A with Mem
Bit(s) Test B with Mem
Clear Bit(s) in Mem
Set Bit(s) in Mem
Branch if Bit(s) Clear
Branch if Bit(s) Set
Mnemonic IMM DIR EXT IX
*
*
*
*
BITA
BITB
*
*
*
*
*
*
BCLR
BSET
*
*
*
*
BRCLR
*
*
BRSET
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
IY
*
*
*
*
*
*
68
17
Shifts and Rotates
Function
Arithm Shift Left Mem
Arithm Shift Left A
Arithm Shift Left B
Arithm Shift Left Double
Arithm Shift Right Mem
Arithm Shift Right A
Arithm Shift Right B
(Logical Shift Left Mem)
(Logical Shift Left A)
(Logical Shift Left B)
(Logical Shift Left Dou)
Mnemonic IMM DIR EXT
*
ASL
ASLA
ASLB
ASLD
*
ASR
ASRA
ASRB
(LSL)
*
(LSLA)
(LSLB)
(LSLD)
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
Shifts and Rotates
IX IY INH
* *
*
*
*
* *
*
*
* *
*
*
*
69
Function
Logical Shift Right Mem
Logical Shift Right A
Logical Shift Right B
Logical Shift Right Dou
Rotate Left Mem
Rotate Left A
Rotate Left B
Rotate Right Mem
Rotate Right A
Rotate Right B
Mnemonic IMM DIR EXT
LSR
*
LSRA
LSRB
LSRD
*
ROL
ROLA
ROLB
*
ROR
RORA
RORB
IX IY INH
* *
*
*
*
* *
*
*
* *
*
*
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
70
Alarm Application
Shift and
Rotate
Instructions
Problem: A set of 8 alarm sensors are connected
to port C Count how many alarm sensors are
activated
NOTE: The address of port C is $1003
* Count the number of alarm sensors that are on.
ORG $E000 ;start address of program
CLC
;make sure that bit C is initially off
CLRB
;make sure that ACCB is initially zero
LDAA $1003 ;get alarm inputs from port C
*
;and load them into ACCA
... continue next slide
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
71
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
72
18
Alarm Application
Stack and Index Register Instructions
* Shift bits into ACCA (port C data) eight times and increment ACCB
* each time a high bit is found (by adding with carry).
How many
LSLA
;C = PC7
alarm
ADCB #$00 ;add 1 if C set
LSLA
;C = PC6
sensors
ADCB #$00 ;add 1 if C set
are
LSLA
;C = PC5
activated?
ADCB #$00 ;add 1 if C set
LSLA
;C = PC4
LSLA
;C = PC3
ADCB #$00 ;add 1 if C set
ADCB #$00 ;add 1 if C set
LSLA
;C = PC2
ADCB #$00 ;add 1 if C set
LSLA
;C = PC1
ADCB #$00 ;add 1 if C set
LSLA
;C = PC0
ADCB #$00 ;add 1 if C set
BRA
*
;stop program
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
Function
Add Accum B to X
Add Accum B to Y
Compare X to Mem (16b)
Compare Y to Mem (16b)
Decrement Stack Pointer
Decrement Index Reg X
Decrement Index Reg Y
Increment Stack Pointer
Increment Index Reg X
Increment Index Reg Y
Load Index Reg X
Load Index Reg Y
Load Stack Pointer
73
Stack and Index Register Instructions
Function
Pull X from Stack
Pull Y from Stack
Push X onto Stack
Push Y onto Stack
Store Index Reg X
Store Index Reg Y
Store Stack Pointer
Transfer SP to X
Transfer SP to Y
Transfer X to SP
Transfer Y to SP
Exchange D with X
Exchange D with Y
Mnemonic
PULX
PULY
PSHX
PSHY
STX
STY
STS
TSX
TSY
TXS
TYS
XGDX
XGDY
IMM DIR EXT IX IY INH
*
*
*
*
*
* *
*
*
*
* *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
74
Condition Code Register Instructions
IMM DIR EXT IX IY INH
*
*
*
*
*
*
*
* *
*
*
*
* *
*
*
*
* *
*
*
*
*
*
*
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
Mnemonic
ABX
ABY
CPX
CPY
DES
DEX
DEY
INS
INX
INY
LDX
LDY
LDS
Function
Clear Carry Bit
Clear Interrupt Mask Bit
Clear Overflow Bit
Set Carry Bit
Set Interrupt Mask Bit
Set Overflow Bit
Transfer A to CCR
Transfer CCR to A
75
Mnemonic
CLC
CLI
CLV
SEC
SEI
SEV
TAP
TPA
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
INH
*
*
*
*
*
*
*
*
76
19
Function
Branch if C Clear
Branch if C Set
Branch if = Zero
Branch if > or =
Branch if >
Branch if Higher
B if Higher or same
Branch if < or =
Branch if Lower
B if Lower or same
Branch if Less Than
Branch if Minus
Branch if not =
Branch if Plus
B if Bit(s) Clear in M
Branch Never
B if Bit(s) Set in Mem
B if Overflow Clear
B if Overflow Set
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BHS
BLE
BLO
BLS
BLT
BMI
BNE
BPL
BRCLR
BRN
BRSET
BVC
BVS
REL DIR IX IY
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* *
*
*
* *
*
*
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
Comments
C=0?
C=1?
Z=1?
Signed >=
Signed >
Unsigned >
Unsigned >=
Signed <=
Unsigned <
Unsigned <=
Signed <
N=1?
Z=0?
N=0?
Bit Manipul
3-cycle NOP
Bit Manipul
V=0?
V=1?
Jumps; Subroutine Calls and Returns;
Interrupt Handling; and Others
Function
Jump
;;;
Branch to Subroutine
Jump to Subroutine
Return from Subroutine
;;;
Return from Interrupt
Software Interrupt
Wait for Interrupt
;;;
No Operation (2-cycle)
Stop Clocks
Test
77
Mnemonic REL DIR EXT IX IY INH
JMP
*
*
* *
BSR
JSR
RTS
*
*
*
*
*
*
RTI
SWI
WAI
*
*
*
NOP
STOP
TEST
*
*
*
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
78
Microcontroller Arithmetic and the
CCR
z
Programming
z
z
A.
B.
C.
D.
E.
F.
G.
H.
Assembly and Other Programming Lang.
Source Code, Object Code, and the Assembler
C Language for Microcontrollers
Fetch/Execute Operations of CPU
The Instruction Set and Addressing Modes
68HC11 Instruction Set
Microcontroller Arithmetic and the CCR
Program Flow Control Using Looping &
Branching
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
z
z
z
z
Two’s complement and the sign bit
Carry, overflow, zero, and half carry
Binary-coded-decimal (BCD) arithmetic
Multiplication
Integer division
Fractional division
Floating point numbers
79
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
80
20
Two’s Complement and the Sign Bit
Carry, Overflow, Zero, and Half Carry
z
z
z
z
The MSB of a binary
number is also called
the signed bit
Many 68HC11
instructions treat
bytes as signed
integers
The double
accumulator
instructions assume a
16-bit signed number
A negative result sets
the N flag of CCR to 1
Method 1 for 2’s complement
Ex. A = %11011000
2’s A = 28 - A
%100000000 –
11011000
00101000
Method 2 for 2’s complement
Ex. A = %11011000
2’s(A) = 1’s(A) + 1
1’s(A) = %00100111
1’s(A) + 1 = %00101000
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
81
z
8-bit unsigned addition and subtraction
z
z
z
z
Carry flag (C) indicates a carry or a borrow when
adding or subtracting unsigned 8-bit integers
Half carry (H) is set if there is a carry from bit 3 to
bit 4
Zero flag (Z) is set when the result of the operation
is zero
Comparison: equality when Z = 1
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
82
Carry, Overflow, Zero, and Half Carry
Carry, Overflow, Zero, and Half Carry
z
8-bit signed addition and subtraction
z
z
z
z
Range of operation -128 ($80) to +127 ($7F)
Overflow (V) is set if the result of adding or
subtracting exceeds the range
N is the copy of the MSB
V is different than C
Overflow occurs in the following situations:
+ve plus +ve equals –ve
-ve plus - ve equals +ve
+ve minus - ve equals –ve
-ve minus +ve equals +ve
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
83
Boolean Formulas of CCR for Add and Sub
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
84
21
Binary-Coded-Decimal (BCD)
Arithmetic
z
z
z
z
Binary-Coded-Decimal (BCD)
Arithmetic
BCD is a binary number system that uses 4-bit
binary representation for the decimal digits
BCD binary arithmetic must be adjusted for
valid BCD results
Instruction used for decimal adjust is: DAA
DAA must follow immediately the arithmetic
instruction (ABA, ADD, or ADC)
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
85
Multiplication: MUL unsigned
A
B
8-bit unsigned
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
Unsigned Integer Division: IDIV
8-bit unsigned
D
X
16-bit unsigned
numerator
16-bit unsigned
denominator
X
/
D
D
X
16-bit unsigned
quotient
The carry flag allows rounding the most significant byte of
the result through the sequence: MUL, ADCA #0
16-bit unsigned
16-bit unsigned
remainder
Condition codes
Z: set if result is $0000; cleared otherwise
V: 0, cleared
C: set if denominator was $0000; cleared otherwise
Condition codes: C set if bit 7 of the result (ACCB) is set;
cleared otherwise
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
86
87
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
88
22
Unsigned Fractional Divide: FDIV
Unsigned Fractional Divide: FDIV
z
D
X
16-bit unsigned
z
16-bit unsigned
numerator
denominator
z
/
D
X
quotient
16-bit unsigned
16-bit unsigned
z
remainder
z
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
Assumption: numerator <
denominator
The radix point is to the left
of bit 15 for the quotient
In case of overflow the
quotient is set to $FFFF =>
0.99998
The remainder can be
resolved into a binaryweighted fraction
A result of $0001 =>
0.000015; and $FFFF =>
0.99998
89
z
z
z
z
Condition codes
Z: set if result is $0000;
cleared otherwise
V: set if denominator was
less than or equal to the
numerator; cleared otherwise
C: set if denominator was
$0000; cleared otherwise
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
90
Floating Point Numbers
Programming
A.
B.
C.
D.
E.
F.
G.
H.
Assembly and Other Programming Lang.
Source Code, Object Code, and the Assembler
C Language for Microcontrollers
Fetch/Execute Operations of CPU
The Instruction Set and Addressing Modes
68HC11 Instruction Set
Microcontroller Arithmetic and the CCR
Program Flow Control Using Looping &
Branching
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
92
91
23
Program Flow Control Using Looping
and Branching
z
z
z
z
z
z
Flow Control
Flow control
Conditional branches
Relative addressing
Secondary memory reference instructions
Jump instructions
Relocatable programs
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
The flow control
structures showed
in the figures are
easy to program using
assembly language
In high-level languages,
there are variations of
these structures.
93
Conditional Branches
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
Conditional Branches. If-Else
* Listing 2.11
* Demonstrate branch instructions
* BEQ - Check if Z = 0
* If ($00) is zero then skip next two instructions
*
else load ($01) and store it in ($00)
* BRA - It's always true!
* If true then execute itself again.
* Listing 2.12
* Demonstrate if-else
* if carry set then write 'T' to $00
*
else write 'F' to $00
* in this case, we define TRUE to be condition when carry
* is set and we define FALSE to be when carry is not set
ORG
LDAA
BEQ
LDAB
STAB
THERE STAA
HERE BRA
ORG
BCS
FALSE LDAB
BRA
*
TRUE LDAB
SKIP STAB
HERE BRA
$E000
$00
THERE
$01
$00
$01
HERE
;start address
;if ACCA == 0 branch to THERE
;($01) -> ($00)
;when ACCA not 0
;($00) -> ($01)
;always branch to HERE
When the conditional branches are used it is important
to ensure that the CCR is not corrupted before ex. the branch
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
94
95
$E000
TRUE ;true if C set
'F'
;else false if C clear
SKIP ;and skip next
;instruction
'T'
;executed if true (C=1)
$00
;store appropriate result
HERE ;stop program
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
96
24
Conditional Branches. If-Else
Conditional Branches. If-Else
* ----------------------------------------------------ORG $E000
LDX
#$C000;initialize src pointer
LDY
#$C500;initialize dst pointer
LDAB #$10 ;initialize counter
DOWH LDAA $00,X ;move byte from src
STAA $00,Y ;to dst
INX
;increment src pointer
INY
;increment dst pointer
DECB
;decrement count, to
*
;indicate another move
BNE
DOWH ;Do-while count not zero
HERE BRA
HERE ;stop program when done
* Demonstrate a do-while (DOWH) loop
* Move 16 bytes starting at address $C000 to a block
* at address $C500. Use the following strategy.
*
do a transfer of a byte while counter is not zero
* We also introduce some common entities, counters and
* pointers. In this case, ACCB is a counter
* IX is a source (src) pointer and IY is a destination (dst)
* pointer. When we say "move," it really means "copy"!
* This sample is source code only.
* Corresponding machine code is not shown.
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
97
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
Secondary Memory Reference
Instructions
Relative Addressing
z
PCnew = PCold + T + rr
rr = PCnew – PCold - T
z
z
Note: relative address is signed and you must extend
the sign when adding or subtracting to 16-bit numbers
z
The absolute 16-bit addresses are unsigned
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
98
99
Many I/O operations
rely on whether
certain bits are set or
cleared
Branch if Bit(s) set:
BRSET
Branch if Bit(s) clear:
BRCLR
A special byte in the
instruction called
mask specifies which
bits to check
LDX #$1000
BRSET $03,X $07 TRUE_IF_SET
BRCLR $03,X $01 TRUE_IF_CLR
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
100
25
Jump Instructions
Relocatable Programs
z
START CBA
BEQ
JMP
SKIP INCA
SKIP
NOT_EQUAL
z
z
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
101
A relocatable program is
one that can start
anywhere in memory
without changing the
machine code
Branch instructions are
relocatable because
their address is relative
to their instruction itself
Jump instructions are
not relocatable
z
z
Relocatability is not
important for program
executing in ROM
Programs executing in
RAM must be
relocatable since the OS
could load them
anywhere
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
102
Assignments
z
z
Chapter 2. Exercises 1 to 4; and 13 to 22
Note: Study Chapter 1 to 2 from Spasov book
for the quiz
ENGG4640/3640; Fall 2004; Prepared by: Radu Muresan
103
26