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HyPPI
The End or The Rebirth
of
MOORE’S LAW
Shuai sun
Volker sorger
Moore's
Law
system
Transistors double every 24
months.
Gordon Moore
— Moore’s Law
Transistors get smaller; power
density stays constant.
— Dennard Scaling
• Slowing down recently
• Ends after 5nm when quantum and
thermodynamic effects come in
• Clock frequency related
• Broke down in 2006
• Speed domain scaling ends
Robert Dennard
The cost of a chip fab doubles
every 4 years.
— Rock’s Law
Arthur Rock
• Hard to maintain transistor/fab cost
Post-Moore Era
• Multicores
− Clock speed stops growing
− Demand for higher performance
− Dark silicon (power, heat)
• Lithography
− Cost reduction
− Larger silicon wafers
− Double/Triple/Quadruple
patterning
What we need:
Novel interconnect options
“35 Years of Microprocessor Trend Data”, M. Horowitz, F.
Labonte, O. Shacham, K. Olukotun, L. Hammond, and C. Batten.
Later.
Novel Interconnect Options
Photonics
(Passive devices for Propagation)
Q Diffraction Limited (>λ/2)
Q Large Footprint (μm2～mm2)
Q Low LMI → High Power (pJ)
R Long Propagation (cm)
Plasmonics
Hybrid
(Active devices for Manipulation)
R No Diffraction Limit (< λ/2)
R Area Efficient (nm2～μm2)
R Energy Efficient (fJ)
Q Short Propagation (μm)
R High On-chip Scaling
R Footprint Reduced
R Power Budget Friendly
R Long Range Communication
Plasmonics
Photonics
Scaling
C. Ye, et al. “λ-size ITO and graphene-based electro-optic
modulators on SOI,” IEEE J. Sel. Topics Quantum Electron,
2014.
Project Top view
Approach



Analyze devices & waveguides options
based on latency, energy efficiency,
area and loss
Simulate waveguide crosstalk and
propagation length under different
scaling
Plug the best devices into interconnect
options
* BFD: Bit Flow Density [Gbps/um2]
Electrical
Plasmonic
Results




Hybrid Photonic Plasmonic
Interconnects (HyPPIs) show the best
potential
10× energy/bit, 100× latency and
throughput improvement comparing
with electrical links
1~3 orders higher Bit Flow Density
Broader CLEAR range
low
BFD
Photonic
HyPPI
(this work)
High
BFD
Mid
BFD
S. Sun, et al. "The Case for Hybrid Photonic Plasmonic Interconnects
(HyPPIs): Low-Latency Energy-and-Area-Efficient On-Chip Interconnects”.
IEEE Photonics Journal, 2015.
2 kinds of HyPPI
HyPPI-Extrinsic: Source
Waveguide
Modulator
Waveguide
Detector
Driver
C.W.
Laser
HyPPI-Intrinsic:
Source (Driver)
Modulator
Waveguide
Detector
Detector
Driver
Laser
Detector
Link Performance
Results
 The electric capacitive delay
Point-to-point latency
Energy Efficiency
hinders efficient links beyond
10’s of um distance.

Electrical-optical break-even
length at about 5-100 um.

Pure plasmonic solutions do not
provide significant improvement
over electronics and photonics.

Pure photonic solution is more
suitable for long range
communication.

Hybridization enables flat length
scaling due to low loss photonic
waveguide and robust data-size
up scaling potential.
Link Throughput
Energy Delay Product
Shuai Sun, and Volker J. Sorger. "Photonic-Plasmonic Hybrid
Interconnects: a Low-latency Energy and Footprint Efficient Link."
Integrated Photonics Research, Silicon and Nanophotonics. OSA, 2015.
Capability-to-LatencyBit Flow Density (BFD)
Energy-Area Ratio
(CLEAR)
Plasmonic
Photonic
Normalized
BFD
(Gbps/μm2)
HyPPI
Extrinsic
HyPPI
Intrinsic
CLEAR =
(Total Throughput)
BFD =
(Chip Area)
=
(# Links) ∙ (Throughput/link)
(Chip Width) ∙ (Chip Length)
Performance
Cost
Capacity × Distance
=
Latency × Energy × Area
Sun, Shuai, et al. "Low latency, area, and energy efficient Hybrid Photonic
Plasmonic on-chip Interconnects (HyPPI)." SPIE OPTO. International
Society for Optics and Photonics, 2016.
Takeaway
Photonic IC
• Hard to be integrated
• Long propagation length
• Ultrafast
Plasmonic IC
• Hard to propagate further
Electrical IC
• The best for 20μm and shorter
• Performance ∝ Length-1
HyPPI
• The best for 20μm and longer
• Combine with Electrical to
provide the best performance
through the entire chip range
Related Works and Awards
Journal
Patent
▪ Shuai Sun, et al. “The Case for Hybrid Photonic
Plasmonic Interconnects (HyPPI): A low Latency, Energy
and Area Efficient On-chip Interconnects”, IEEE
Photonics Journal, Sep 2015.
▪ Provisional U.S. Patent: “Hybrid Photonic Plasmonic
Interconnects (HyPPI) with intrinsic and extrinsic
modulation options.” S. Sun, V. J. Sorger, T. ElGhazawi, V. Narayana, A.-H. Badawy (2015).
Proceedings
Awards
▪ Sun, Shuai, et al. "Low latency, area, and energy efficient
Hybrid Photonic Plasmonic on-chip Interconnects
(HyPPI)." SPIE OPTO. International Society for Optics
and Photonics, 2016.
▪ Shuai Sun, et al. "Bit Flow Density (BFD): An Effective
Performance FOM for Optical On-chip Interconnects."
Laser Science to Photonic Applications (CLEO: 2016).
(Submitted).
▪ Shuai Sun, and Volker J. Sorger. "Photonic-Plasmonic
Hybrid Interconnects: a Low-latency Energy and
Footprint Efficient Link." Integrated Photonics Research,
Silicon and Nanophotonics. OSA, 2015.
▪ GW Research Days 2016 2nd prize for Graduate
Presenters in the area of Engineering
▪ SEAS 2016 R&D Showcase the 2nd prize of the
Theoretical Research Award
▪ SEAS 2016 R&D Showcase the 2nd prize of the
Entrepreneurship Award
Further info &
Acknowledgement
• Universal on-chip FOM (CLEAR)
• Dynamic controlled hybrid networks
• Photonic Moore’s Law roadmap
• …
OPEN Lab: sorger.seas.gwu.edu
This project is supported by the Air Force Office
of Scientific Research (AFOSR), award number
FA9550-15-1-0447. PI: Tarek El-Ghazawi, CoPI:
Volker Sorger, Vikram Narayana.
Shuai SUN
[email protected]