Download Chapter # 4: Programmable and Steering Logic Contemporary Logic

Contemporary Logic Design
Prog. & Steering Logic
Chapter # 4: Programmable and
Steering Logic
Section 4.2
© R.H. Katz Transparency No. 8-1
Contemporary Logic Design
Prog. & Steering Logic
Non-Gate Logic
Introduction
AND-OR-Invert
PAL/PLA
Generalized Building Blocks
Beyond Simple Gates
Kinds of "Non-gate logic":
• switching circuits built from CMOS transmission gates
• multiplexer/selecter functions
• decoders
• tri-state and open collector gates
• read-only memories
© R.H. Katz Transparency No. 8-2
Contemporary Logic Design
Prog. & Steering Logic
Multiplexers/Selectors
Use of Multiplexers/Selectors
Multi-point connections
A0
A1
B0
B1
Multiple input sources
Sa
MUX
MUX
A
B
Sb
Sum
Ss
DEMUX
S0
Multiple output destinations
S1
Mux: Chooses one of many inputs to steer to its single output under direction of
control inputs
DeMux: Takes single data input and steers it to one of its many outputs under the
direction of its control inputs
© R.H. Katz Transparency No. 8-3
Steering Logic
Contemporary Logic Design
Prog. & Steering Logic
Use of Multiplexer/Demultiplexer in Digital Systems
A
Demultiplex ers
Y
Multiplex ers
B
Z
A
Y
Demultiplex ers
B
Multiplex ers
Z
So far, we've only seen point-to-point connections among gates
Mux/Demux used to implement multiple source/multiple destination
interconnect
© R.H. Katz Transparency No. 8-4
Multiplexers/Selectors
I0
2:1
mux
I1
Contemporary Logic Design
Prog. & Steering Logic
Named by the number of
data inputs and number of data outputs
Z
Z = A' I 0 + A I1
A
I0
I1
I2
I3
4:1
mux
A
I0
I1
I2
I3
Z
B
8:1
mux
I4
I5
I6
I7
A
Z = A' B' I0 + A' B I1 + A B' I2 + A B I3
B
Z
C
Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 +
A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7
n -1
2
In general, Z = S
m I
k=0
k k
in minterm shorthand form for a 2 n :1 Mux
© R.H. Katz Transparency No. 8-5
Contemporary Logic Design
Prog. & Steering Logic
Multiplexers/Selectors
General Concept
2
n
data inputs, n control inputs, 1 output
n
used to connect 2 points to a single point
control signal pattern form binary index of input connected to output
Z = A' I 0 + A I 1
A
0
1
Functional form
Logical form
Z
I0
I1
I1
0
0
0
0
1
1
1
1
I0
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
Z
0
0
1
0
0
1
1
1
Two alternative forms
for a 2:1 Mux Truth Table
© R.H. Katz Transparency No. 8-6
Contemporary Logic Design
Prog. & Steering Logic
Multiplexers/Selectors
Alternative Implementations
I0
I1
Z
I2
I3
A
B
Gate Level
Implementation
of 4:1 Mux
thirty six transistors
© R.H. Katz Transparency No. 8-7
Contemporary Logic Design
Multiplexer/Selector
Prog. & Steering Logic
Large multiplexers can be implemented by cascaded smaller ones
I0
I1
I2
I3
0 4:1
1 mux
2
3 S1 S0
I4
I5
I6
I7
0 4:1
1 mux
2
3 S1 S0
B
Control signals B and C simultaneously
choose one of I0-I3 and I4-I7
8:1
mux
0 2:1
mux
1 S
C
Z
Control signal A chooses which of the
upper or lower MUX's output to gate to Z
A
© R.H. Katz Transparency No. 8-8
Contemporary Logic Design
Prog. & Steering Logic
Multiplexer/Selector
Alternative 8:1 Mux Implementation
I0
0
I1
1 S
C
I2
0
I3
1 S
0
1
C
I4
0
I5
1 S
3
C
I6
0
I7
1 S
Z
2
S1
S0
A
B
C
© R.H. Katz Transparency No. 8-9
Contemporary Logic Design
Prog. & Steering Logic
Multiplexer/Selector
Multiplexers/selectors as a general purpose logic block
n-1
2
:1 multiplexer can implement any function of n variables
n-1 control variables; remaining variable is a data input to the mux
Example: Implement as (1) 8:1 MUX and (2) 4:1 MUX
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C
= A' B' (C') + A' B (C') + A B' (0) + A B (1)
(1)
1
0
1
0
0
0
1
1
0
1
2
3
4
5
6
7
(2)
F
8:1
MUX
S2 S1 S0
A
B
C
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
1
0
1
0
0
0
1
1
C
C
C
C
0
1
0
0
1
2
3
4:1
MUX
S1
A
F
S0
B
1
"Lookup Table"
© R.H. Katz Transparency No. 8-10
Contemporary Logic Design
Prog. & Steering Logic
Multiplexer/Selector
Generalization
I 1 I 2 … In
n-1 Mux
control variables
single Mux
data variable
…
0
1
F
0
0
0
1
1
0
1
1
Four possible
configurations
of the truth table rows
0
In
In
1
Can be expressed as
a function of In, 0, 1
© R.H. Katz Transparency No. 8-11
Contemporary Logic Design
Prog. & Steering Logic
Multiplexer/Selector
Example:
G(A,B,C,D) can be implemented by an 8:1 MUX:
AB
CD 00
01
11
10
1
0
1
1
1
0
0
0
1
D
0
1
D
D
D
D
K-map
Choose A,B,C
as control variables
D
C
1
1
0
1
0
1
1
0
B
Multiplexer
Implementation
TTL package efficient
May be gate inefficient
0
1
2
3
4
5
6
7
G
8:1
mux
S2
S1
A
B
S0
C
G = A’B’C’(1) + A’B’C(D) + A’BC’(0) + A’BC(1) + AB’C’(D’) + AB’C(D)
+ ABC’(D’) + ABC(D’)
© R.H. Katz Transparency No. 8-12
Contemporary Logic Design
Prog. & Steering Logic
Decoders/Demultiplexers
Decoder: single data input, n control inputs, 2
n
outputs
control inputs (called select S) represent Binary index of output to which
the input is connected
data input usually called "enable" (G)
named by the number of control signals and number of output signals
1:2 Decoder: (2 outputs)
O0 = G • S; O1 = G • S
2:4 Decoder: (4 outputs)
O0 = G • S0 • S1
3:8 Decoder: (8 outputs)
O0 = G • S0 • S1 • S2
O1 = G • S0 • S1 • S2
O2 = G • S0 • S1 • S2
O1 = G • S0 • S1
O3 = G • S0 • S1 • S2
O2 = G • S0 • S1
O4 = G • S0 • S1 • S2
O3 = G • S0 • S1
O5 = G • S0 • S1 • S2
O6 = G • S0 • S1 • S2
O7 = G • S0 • S1 • S2
© R.H. Katz Transparency No. 8-13
Contemporary Logic Design
Prog. & Steering Logic
Decoders/Demultiplexers
Alternative Implementations
G
Output0
Select
/G
Select
Output0
Output1
Output1
1:2 Decoder, Active Low Enable
1:2 Decoder, Active High Enable
/G
G
Select0
Output0
Output0
Output1
Output1
Output2
Output2
Output3
Output3
Select1
2:4 Decoder, Active High Enable
Select0
Select1
2:4 Decoder, Active Low Enable
© R.H. Katz Transparency No. 8-14
Decoder/Demultiplexer
Decoder as a Logic Building Block
Enb
3:8
dec
S2
A
S1
B
S0
0
1
2
3
4
5
6
7
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
Contemporary Logic Design
Prog. & Steering Logic
Decoder Generates Appropriate
Minterm based on Control Signals
C
© R.H. Katz Transparency No. 8-15
Decoder/Demultiplexer
Decoder as a Logic Building Block
Example Function: F(A,B,C,D)
Contemporary Logic Design
Prog. & Steering Logic
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')
It is more convenient to reexpress the functions in their canonical sum
of products form.
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B CD’ + ABCD
F3 = (ABCD)’
© R.H. Katz Transparency No. 8-16
Decoder/Demultiplexer
Decoder as a Logic Building Block
Example Function: F(A,B,C,D)
A B C D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Contemporary Logic Design
Prog. & Steering Logic
F1 F2 F3
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
© R.H. Katz Transparency No. 8-17
Contemporary Logic Design
Prog. & Steering Logic
Decoder/Demultiplexer
Decoder as a Logic Building Block
Enb
4:16
dec
S3 S2 S1 S0
A
B C
D
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A B CD
A B CD
A B CD
A B CD
A B CD
A B CD
A B CD
A B CD
A B CD
A B CD
A B CD
A B CD
AB
AB
AB
AB
F1
F2
CD
CD
CD
CD
F3
If active low enable, then use NAND gates!
F1 = A’BC’D + A’B’CD + ABCD
F2 = ABC’D + ABCD’ + ABCD
F3 = (ABCD)’
© R.H. Katz Transparency No. 8-18
Contemporary Logic Design
Prog. & Steering Logic
Decoder/Demultiplexer
G’
B
A
YO’
Y1’
Y2’
Y3’
H
X
X
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
L
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
L
Active Low Output Decoder
© R.H. Katz Transparency No. 8-19
Contemporary Logic Design
Prog. & Steering Logic
Multiplexers/Decoders
5:32 Decoder
\EN
S4
S3
1G 1Y3
139 1Y2
1B 1Y1
1A 1Y0
2G 2Y3
2Y2
2B 2Y1
2A 2Y0
\EN
S2
S1
S0
\Y31
5:32
Decoder
Subsystem
.
.
.
S2
S1
S0
\Y0
S4 S3 S2 S1 S0
S2
S1
S0
S2
S1
S0
G1
G2A
G2B
Y7
Y6
Y5
Y4
138 Y3
Y2
C
Y1
B
Y0
A
\Y31
\Y30
\Y29
\Y28
\Y27
\Y26
\Y25
\Y24
Y7
G1
G2A Y6
G2B Y5
138 Y4
Y3
Y2
C
Y1
B
Y0
A
\Y23
\Y22
\Y21
\Y20
\Y19
\Y18
\Y17
\Y16
Y7
G1
G2A Y6
G2B Y5
138 Y4
Y3
C
Y2
B
Y1
A
Y0
\Y15
\Y14
\Y13
\Y12
\Y11
\Y10
\Y9
\Y8
G1 Y7
G2A Y6
G2B Y5
138 Y4
Y3
Y2
C
Y1
B
Y0
A
\Y7
\Y6
\Y5
\Y4
\Y3
\Y2
\Y1
\Y0
© R.H. Katz Transparency No. 8-20
Contemporary Logic Design
Prog. & Steering Logic
Read-Only Memories
ROM: Two dimensional array of 1's and 0's
Internal storage elements of the ROM are set to their values once.
After that are read only or may be erased and rewritten at a later time.
Row is called a "word";
Index selected by control inputs is called an "address"
Width of row is called bit-width or wordsize
Address is input, selected word is output
+5 V +5 V +5 V +5 V
n
2 -1
Dec
i
Word Line 001 1
j
Word Line 101 0
Internal Organization
0
0
n-1
Address
Bit Line s
© R.H. Katz Transparency No. 8-21
Contemporary Logic Design
Prog. & Steering Logic
Read-Only Memories
Memory array
Not unlike a PLA
structure with a
fully decoded
AND array!
Decoder
2n w ord
lines
2n w ords by
m bits
m output
lines
n addres s
lines
ROM vs. PLA:
ROM approach advantageous when
(1) design time is short (no need to minimize output functions)
(2) most input combinations are needed (e.g., code converters)
(3) little sharing of product terms among output functions
ROM problem: size doubles for each additional input, can't use don't cares
PLA approach advantangeous when
(1) design tool like espresso is available
(2) there are relatively few unique minterm combinations
(3) many minterms are shared among the output functions
PAL problem: constrained fan-ins on OR planes
© R.H. Katz Transparency No. 8-22
Contemporary Logic Design
Prog. & Steering Logic
Read-Only Memories
Example: Combination Logic Implementation
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
Addres s
ROM
8 words ¥by
4 bits
A B C
addres s
F0
F1
F2
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F0
0
1
0
0
1
1
0
0
F1
0
1
1
0
0
0
0
1
F2
1
1
0
0
1
0
0
0
F3
0
0
0
1
1
0
1
0
Word Contents
F3
outputs
© R.H. Katz Transparency No. 8-23
Contemporary Logic Design
Prog. & Steering Logic
Read-Only Memories
2764 EPROM
8K x 8
2764
VPP
PGM
A12
A11
A10 O7
A9
O6
A8
O5
A7
O4
A6
O3
A5
O2
A4
O1
A3
O0
A2
A1
A0
CS
OE
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U3
OE
+
A13
/OE
A12:A0
D15:D8
D7:D0
+
16K x 16
Subsystem
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U1
OE
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U2
OE
+
+
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U0
OE
buses -- several logically related wires that
share a common function.
© R.H. Katz Transparency No. 8-24
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic: Switches
Voltage Controlled Switches
Gate
Channel
Region
Oxide
Source
Drain
Silicon Bulk
n-type Si
p-type Si
"n-Channel MOS"
Metal Gate, Oxide, Silicon Sandwich
Diffusion regions: negatively charged ions driven into Si surface
Si Bulk: positively charged ions
By "pulling" electrons to the surface, a conducting channel is
formed
© R.H. Katz Transparency No. 8-25
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic
Voltage Controlled Switches
Gate
Source
Drain
Logic 1 on gate,
Source and Drain connected
nMOS Transistor
Gate
Source
Logic 0 on gate,
Source and Drain connected
Drain
pMOS Transistor
© R.H. Katz Transparency No. 8-26
Steering Logic
Contemporary Logic Design
Prog. & Steering Logic
• CMOS transmission gate is constructed from a
normally open switch (nmos transistor) wired in
parallel with a normally closed switch (pmos
transistor), with complementary control signals
© R.H. Katz Transparency No. 8-27
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic
Transmission gates provide an efficient way to build steering logic.
Steering logic circuits route data inputs to outputs based on the settig of control signals.
Logic Gates from Switches
+5V
A
B
A
+5V
A
B
+5V
AB
A
A+ B
Inverter
NAND Gate
NOR Gate
Pull-up network constructed from pMOS transistors
Pull-down network constructed from nMOS transistors
© R.H. Katz Transparency No. 8-28
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic
Inverter Operation
+5V
"1"
+5V
"0"
Input is 1
Pull-up does not conduct
Pull-down conducts
Output connected to GND
"0"
"1"
Input is 0
Pull-up conducts
Pull-down does not conduct
Output connected to VDD
© R.H. Katz Transparency No. 8-29
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic
NAND Gate Operation
"1"
"0"
"1"
+5V
"1"
+5V
"0"
A = 1, B = 1
Pull-up network does not conduct
Pull-down network conducts
Output node connected to GND
"1"
A = 0, B = 1
Pull-up network has path to VDD
Pull-down network path broken
Output node connected to VDD
© R.H. Katz Transparency No. 8-30
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic
NOR Gate Operation
"0"
+5V
"1"
"0"
+5V
"1"
A = 0, B = 0
Pull-up network conducts
Pull-down network broken
Output node at VDD
"0"
"0"
A = 1, B = 0
Pull-up network broken
Pull-down network conducts
Output node at GND
© R.H. Katz Transparency No. 8-31
Contemporary Logic Design
Prog. & Steering Logic
Read Appendix B.4 --- MOS Transistors, p. 675-681
© R.H. Katz Transparency No. 8-32
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic
CMOS Transmission Gate
nMOS transistors good at passing 0's but bad at passing 1's
pMOS transistors good at passing 1's but bad at passing 0's
perfect "transmission" gate places these in parallel:
Control
Control
In
Out
Control
Switches
In
Control
Out
Control
Transistors
In
Out
Control
Transmission or
"Butterfly" Gate
© R.H. Katz Transparency No. 8-33
Contemporary Logic Design
Steering Logic
Prog. & Steering Logic
Selection Function/Demultiplexer Function with Transmission Gates
S
Selector:
Choose I0 if S = 0
Choose I1 if S = 1
I
0
S
I
Z
S
1
S
S
Demultiplexer:
I to Z0 if S = 0
I to Z1 if S = 1
Z0
I
S
S
Z1
S
© R.H. Katz Transparency No. 8-34
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic
Well-formed Switching Networks
Problem with the Demux implementation:
multiple outputs, but only one connected to the input!
S
Z0
S
"0"
I
S
S
Z1
S
"0"
S
The fix: additional logic to drive every output to a known value
Never allow outputs to "float"
© R.H. Katz Transparency No. 8-35
Contemporary Logic Design
Prog. & Steering Logic
Decoders/Demultiplexers
Switch Logic Implementations
Select
Select
G
G
Output
Output
Select
Select
0
Select
Select
0
"0"
Select
Output
1
Select
Select
Output
1
Select
Naive, Incorrect Implementation
Select
All outputs not driven at all times
"0"
Select
Correct 1:2 Decoder Implementation
© R.H. Katz Transparency No. 8-36
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic
Complex Steering Logic Example
N Input Tally Circuit: count # of 1's in the inputs
N+1 Outputs
I
1
0
1
I1
Zero
One
1
0
0
1
Zero
One
Conventional Logic
for 1 Input Tally
Function
© R.H. Katz Transparency No. 8-37
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic
I1
Straight Through
I1
"0"
One
"0"
One
"1"
Zero
Diagonal
"0"
"1"
Zero
"0"
Switch Logic Implementation
of Tally Function
© R.H. Katz Transparency No. 8-38
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic
Complex Steering Logic Example
Operation of the 1 Input Tally Circuit
"0"
"0"
One
"0"
"0"
One
"1"
Zero
"0"
"1"
Zero
"0"
Input is 0, straight through switches enabled
© R.H. Katz Transparency No. 8-39
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic
Complex Steering Logic Example
Operation of 1 input Tally Circuit
"1"
"0"
"1"
One
Zero
"1"
"0"
One
"1"
Zero
"0"
"0"
Input = 1, diagonal switches enabled
© R.H. Katz Transparency No. 8-40
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic
Complex Steering Logic Example
Extension to the 2-input case
I 1 I2
0
0
1
1
0
1
0
1
Zero One Tw o
1
0
0
0
0
1
1
0
0
0
0
1
I1
Zero
I2
One
Tw o
Conventional logic implementation
Switching Network -- 24 transistors
Gate Method -- 26 transistors
© R.H. Katz Transparency No. 8-41
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic
Complex Steering Logic Example
Switch Logic Implementation: 2-input Tally Circuit
I2
I2
I1
"0"
Two
"0"
"1"
"0"
I1
"0"
One
"0"
One
Zero
Two
One
Zero
"0"
One
Cascade the 1-input implementation!
"1"
"0"
Zero
Zero
"0"
© R.H. Katz Transparency No. 8-42
Contemporary Logic Design
Prog. & Steering Logic
Steering Logic
Complex Steering Logic Example
Operation of 2-input implementation
(a) I1=0, I2=0
(b) I1=1, I2=0
"0"
"0"
"0"
"1"
"0"
"1"
"0"
One
"0"
Zero
"1"
"0"
"1"
"0"
(b) I1=0, I2=1
One
Zero
"0"
One
"0"
"1"
Zero
"0"
"0"
"0"
"0"
"0"
"1"
"0"
"0"
"0"
"1"
"0"
"0"
"1"
"0"
"1"
"1"
"0"
"0"
"1"
"0"
One
Zero
"0"
"0"
(d) I1=1, I2=1
© R.H. Katz Transparency No. 8-43
"1"
"0"
"0"
Decoders/Demultiplexers
Switch Implementation of 2:4 Decoder
Select
G
0
Select
1
Output
0
Operation of 2:4 Decoder
"0"
"0"
G
S0 = 0, S1 = 0
Output
1
"0"
one straight thru path
three diagonal paths
"0"
G
Contemporary Logic Design
Prog. & Steering Logic
Output
2
"0"
"0"
G
Output
3
"0"
"0"
© R.H. Katz Transparency No. 8-44
Contemporary Logic Design
Multiplexers/Selectors
Prog. & Steering Logic
Alternative Implementations -- Transmission Gates
A
B
I0
Z
I1
I2
I3
Transmission Gate
Implementation of
4:1 Mux
twenty transistors
© R.H. Katz Transparency No. 8-45
Contemporary Logic Design
Tri-State and Open-Collector
Prog. & Steering Logic
The Third State
Logic States: "0", "1"
Don't Care/Don't Know State: "X" (must be some value in real circuit!)
Third State: "Z" — high impedance — infinite resistance, no connection
Tri-state gates: output values are "0", "1", and "Z"
additional input: output enable (OE)
A OE F
X 0 Z
0 1 0
1 1 1
When OE is high, this gate is a non-inverting "buffer"
When OE is low, it is as though the gate was
disconnected from the output!
This allows more than one gate to be connected to the
same output wire, as long as only one has its
output enabled at the same time
100
Non-inverting buffer's
timing waveform
A
OE
F
"Z"
"Z"
© R.H. Katz Transparency No. 8-46
Contemporary Logic Design
Prog. & Steering Logic
Tri-state and Open Collector
Using tri-state gates to implement an economical multiplexer:
Input
F
0
OE
Input
When SelectInput is asserted high
Input1 is connected to F
1
OE
When SelectInput is driven low
Input0 is connected to F
This is essentially a 2:1 Mux
SelectInput
© R.H. Katz Transparency No. 8-47
Tri-state and Open Collector
Alternative Tri-state Fragment
Input
F
0
OE
Input
Contemporary Logic Design
Prog. & Steering Logic
Active low tri-state enables
plus inverting tri-state buffers
1
OE
SelectInput
© R.H. Katz Transparency No. 8-48
Contemporary Logic Design
Prog. & Steering Logic
Tri-state and Open Collector
Switch Level Implementation of tri-state gate,
inverting with active low enable
1
F
I
OE
0
© R.H. Katz Transparency No. 8-49
Contemporary Logic Design
Prog. & Steering Logic
Tri-State and Open Collector
Open Collector
another way to connect multiple gates to the same output wire
gate only has the ability to pull its output low; it cannot actively
drive the wire high
this is done by pulling the wire up to a logic 1 voltage through a
resistor
+5 V
Pull-up resistor
Open-collec tor
NAND gate
F
0V
A
B
Output is 0 only when A and B are both asserted.
Otherwise node F is floating.
The resistor will pull it up to a logic 1 voltage.
© R.H. Katz Transparency No. 8-50
Contemporary Logic Design
Prog. & Steering Logic
Tri-State and Open Collector
4:1 Multiplexer, Revisited
\EN 1
S1
S0
1G 1Y 3
1Y 2
3 139
1B 1Y 1
2
1A 1Y 0
15
7
6
5
4
D3
9
2G 2Y 3 10
2Y 2
13 2B
2Y 1 11
14 2A
2Y 0 12
D2
D1
D0
Decoder + 4 tri-state Gates
© R.H. Katz Transparency No. 8-51
Contemporary Logic Design
Prog. & Steering Logic
Tri-State and Open Collector
4:1 Multiplexer
\EN 1
Y3
139 Y2
3
Y1
S1
B
2
A
Y0
S0
G
+5V
7
6
5
4
\I3
OR
\I2
OR
\I1
OR
\I0
OR
F
Decoder + 4 Open Collector Gates
© R.H. Katz Transparency No. 8-52
HW#8 Chapter 4: Section 4.2
Contemporary Logic Design
Prog. & Steering Logic
© R.H. Katz Transparency No. 8-53