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Complete OCR Schematic
Ibias
M=0.25
I=0.16nA
vb
vrf
W='10*l'
L='10*l'
v1
W='10*l'
L='10*l'
W='10*l'
L='10*l'
W='10*l'
L='10*l'
vrf
W='10*l'
L='10*l'
W='10*l'
L='10*l'
W='10*l'
L='10*l'
vor
voll
W='10*l'
L='10*l'
W='10*l'
L='10*l'
W='10*l'
L='10*l'
W='10*l'
W='10*l'
L='10*l'
L='10*l'
W='10*l'
L='10*l'
V=1.05
C=10pF
Low 3dB corner frequency established by large Cout and small Gm1 (using small Ibias)
which gives large t. Cascode provides sufficient gain in first stage that is boosted up
by a factor of around 2 in the second stage.
Circuit Block Diagram
Vrf
Vrf
-
+
V1
+
+
Gm1
1/(Gout + sCout)
+
Gm2
I cor
Gm1  Gm 2

V1
(Gout  sCout )
The DC gain of the offset correction circuit is set by Gm1*Ro and the corner frequency
is set by Gm1*Cout. Gm2 is the V-to-I conversion to allow a current feedback into the
original filter OTA.
Icor
Simulation3-f-offset-ac
vm(out)
vm(x)
1
100m
10m
1m
Simulation3-f-offset-ac
vm(out)
vm(x)
1
100m
10m
1m
100u
100u
100m
Voltage Magnitude (V)
Voltage Magnitude (V)
AC Response Verification
1
10
100
1k
Frequency (Hz)
Q=2; f90=300Hz
10k
100k
1M
100m
1
10
100
1k
Frequency (Hz)
Q=2; f90=2kHz
10k
100k
1M
Stability Verification
Simulation3-f-offset
v(out)
v(x)
1.70
1.65
Voltage (V)
1.60
1.55
1.50
1.45
1.40
0.50
0.55
Time (s)
0.60
0.65
DC Behavior and Startup Time
v(out)
v(x)
Voltage (V)
Voltage (V)
Simulation3-f-offset
Simulation3-f-offset-dc
(1.61, 1.58) (1.51, 1.58) dx=104.00m dy=200.00u
1.75
1.70
1.65
1.60
1.55
v(out)
v(x)
1.5
1.0
0.5
1.50
0.0
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
vdc (V)
Time (s)
DC behavior of OCR
Startup time verification
0.9
1.0
Final Results


Q=2, f90=10kHz filter uses 6.13mW (bonus)
f90 variable from 100Hz to 10kHz; Q variable from 1 to 6
 Effective noise sources N=4.81, VL=0.765V which results in
DR > 60dB
 Filter attenuation at HF past f90 = -75dB; < 1dB variation
from unity gain in passband
 Power to correct 10kHz filter = 480.48nW
 Power-on startup time = 0.12s (bonus)
 14 transistors used for OCR circuit (bonus)
 Maximum cap size = 10pF
 Lowest current used = 0.16nA
 Entire layout fits in ¼ of padring area (bonus)
Full Chip Layout