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Chip on Glass Graphic
Display Driver with Lattice
MachXO2 (VHDL)
29 March 2013
Features
The MachXO2 breakout board (Digi-Key Part number 220-1298-ND) is a low cost programmable logic
device (PLD) development board. The MachXO2 is a low power FPGA with a hardened, ASIC-gate
based, embedded function block (EFB). It is worth noting that the device used in this design was a
1200ZE device (Digi-Key Part number 220-1298-ND), it has been replaced by a 7000HE device (DigiKey Part number 220-2625-ND). This design will work with either device. The Newhaven chip on glass
display (Digi-Key Part number NHD-C12864LZ-FSW-FBW-3V3-ND) is interfaced through a custom
board with a capacitor array to support the display’s on-board charge pump. The display is a 128x64
pixel LCD display with a built-in ST7565R-G controller. The following design topics will be covered:
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Chip on glass (COG) graphic display application introduction and overview
Instantiation of VHDL modules in a top-level hierarchy as seen in RTL diagram
Active-HDL Test Bench simulation
COG display state machine overview
Introduction
This reference design uses the MachXO2 low cost FPGA to drive parallel data and control signals
through a custom interface board to a chip on glass graphical display. In many human-machine interface
(HMI) applications displays are commonly used to convey system status and user information.
Background
The MachXO2 breakout board is a low-cost and low-power solution for many input and control
applications.
In this application two state machines are employed to configure the chip on glass display, write
commands and data bits to the display, and control the flow of stored data and commands from a data
ROM to display and scroll the displayed word “Digi-Key” from the top to the bottom of the display. The
display and MachXO2 breakout board can be seen below in figures 1 and 2 with two different display
setting, normal and inverted respectively.
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Figure 1 – Display Normal Setting
Figure 2 – Display Inverted Setting
The data FSM has states for clearing the display, setting the page and column position and either
displaying the image static or continuously scrolling the image. The state flow can be customized by
simply changing the flow of the state machine from the current to the next state. For instance to scroll the
display, state_next within the write_data state is set to scroll. To display a static image, state_next can be
set to static.
The Software required for the design:
 Lattice Diamond Design Software version 2.0.1 with third party software Synplify Pro for Lattice
and Active-HDL Lattice Edition.
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Application
Building the Circuit
The two state machines are synchronized with a two signal handshake. This keeps the Data_FSM from
trying to write to the COG_Parallel_Driver while it is busy. The two signals used in the handshake are
“write_en” from the Data_FSM and “busy” from the COG_Parallel_Driver state machine. See Figure 3
below for an RTL diagram. The hand shake can be seen in simulation below in Figure 4.
Figure 3 – RTL diagram for Chip on Glass Display Driver
Figure 4 – Two Signal Handshake for Synchronization
The test-bench for the simulation is included. The clock period can be varied within the test-bench file.
The on-chip oscillator is not simulated; some signals in the top level file need to be un/commented for
simulation. Refer to the commented ports, signals, instantiations and continuous assignments within the
Chip_on_Glass_Top file for guidance. The design hierarchy can be seen below in Figure 5.
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Figure 5 – Chip on Glass Display Driver Design Hierarchy
The state flow diagram for the COG_Parallel_Driver is seen below in Figure 6.
Figure 6 – State Flow Diagram for COG_Parallel_Driver FSM
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The first 13 states control the initialization of the display. The initialization states include each of the
following:
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Bias control set to 1/9th bias
ADC select set to normal
Com output reverse set to normal
Display all points set to off
Display start line set to X”40”, top line
Internal voltage converter set to on
Internal voltage regulator set to on
Internal voltage follower set to on
Built in resistor ratio set to 6
Middle of range voltage reference mode set to X”81”
Reference voltage resistor set to set to X”09”
Display set to reverse (for inverse display setting)
Set display to on
After it is initialized the display sits in idle until a “write_en” signal is asserted from the Data_FSM. This
will cause the COG_Parallel_Driver FSM to either start a write or command cycle depending on the state
of the RegSel signal from the Data_FSM. A simulated output can be seen in figure 7 and 8 below.
Figure 7 – Aldec Testbench Output for Clearing the Screen
Figure 7 shows the page set and column set commands followed by the write signals used to clear each
page of the display.
Figure 8 – Aldec Testbench Output for Displaying “Digi-Key”
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Figure 8 shows the parallel data stream used to construct the “Digi-Key” word. The Data_FSM can be
altered and customized to display multiple lines of data to construct a graphic, or delete specific sections
of the delay to prepare for new pixel writes. Additional ROM files can be loaded in the same manner as
the existing “Digi-Key” ROM. The pin assignments used in the design can be seen below in Figure 9.
Figure 9 – Pin Assignments for MachXO2
Capabilities, Limitations, and Alterations
Lattice Diamond version 2.0.1 was used to develop this tutorial with supporting software from Synopsis
(Synplify Pro for Lattice) and Aldec (Active-HDL Lattice Edition). Diamond can be used as a stand
alone development environment with alternative synthesis and simulation software.
Conclusion
This reference design demonstrates how to use the Lattice MachXO2 (PLD) to run a Newhaven Chip on
Glass graphic display module. The Data_FSM can easily be modified to drive customized display data
using the carefully commented example given.
Additional Information
Further design support, product tutorials, application notes, user’s guides and other documentation can be
found on the Lattice website at http://www.latticesemi.com/support/index.cfm?source=topnav.
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Appendix:
The complete Lattice Diamond Test Bench Tutorial project can be downloaded from the Digi-Key,
eewiki.net website under the Programmable Logic section.
Disclaimer
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