Download CS 61C: Great Ideas in Computer Architecture (Machine Structures)

CS 61C: Great Ideas in Computer
Architecture (Machine Structures)
Muxes, Adders, and ALUs
Instructors:
Randy H. Katz
David A. Patterson
http://inst.eecs.Berkeley.edu/~cs61c/fa10
4/29/2017
Fall 2010 -- Lecture #24
1
Agenda
•
•
•
•
Multiplexer
Administrivia
Technology Break
ALU Design
4/29/2017
Fall 2010 -- Lecture #24
2
Agenda
•
•
•
•
Multiplexer
Administrivia
Technology Break
ALU Design
4/29/2017
Fall 2010 -- Lecture #24
3
Data Multiplexer
(e.g., 2-to-1 x n-bit-wide)
“mux”
4/29/2017
Fall 2010 -- Lecture #24
4
N Instances of 1-bit-Wide Mux
How many rows in TT?
4/29/2017
Fall 2010 -- Lecture #24
5
How Do We Build a
1-bit-Wide Mux?
4/29/2017
Fall 2010 -- Lecture #24
6
4-to-1 Multiplexer
How many rows in TT?
4/29/2017
Fall 2010 -- Lecture #24
7
Alternative Hierarchical Approach
4/29/2017
Fall 2010 -- Lecture #24
8
Arithmetic and Logic Unit
• Most processors contain a special logic block
called “Arithmetic and Logic Unit” (ALU)
• We’ll show you an easy one that does ADD,
SUB, bitwise AND, bitwise OR
4/29/2017
Fall 2010 -- Lecture #24
9
Simple ALU
4/29/2017
Fall 2010 -- Lecture #24
10
Agenda
•
•
•
•
Mutiplexers
Administrivia
Technology Break
ALU
4/29/2017
Fall 2010 -- Lecture #24
11
Agenda
•
•
•
•
Mux + Adder Design
Administrivia
Technology Break
ALU Design
4/29/2017
Fall 2010 -- Lecture #24
12
Agenda
•
•
•
•
Multiplexer
Administrivia
Technology Break
ALU Design
4/29/2017
Fall 2010 -- Lecture #24
13
Adder/Subtractor: One-bit adder
Least Significant Bit
4/29/2017
Fall 2010 -- Lecture #24
14
Adder/Subtractor: One-bit adder
(1/2) …
4/29/2017
Fall 2010 -- Lecture #24
15
Adder/Subtractor: One-bit Adder
(2/2) …
4/29/2017
Fall 2010 -- Lecture #24
16
N x 1-bit Adders  1 N-bit Adder
Connect Carry Out i-1 to Carry in i:
b0
+
4/29/2017
+
Fall 2010 -- Lecture #24
+
17
Overflow Conditions
Add two positive numbers to get a negative number
or two negative numbers to get a positive number
-1
-2
1111
0001
1101
-4
0010
1100
-5
-4
1001
-7
0110
1000
-8
0111
+5
1110
0010
1011
1010
-6
-7
-7 - 2 = +7!
Fall 2010 -- Lecture #24
0110
1000
-8
+7
+2
0011
+3
0100
+4
0101
1001
+6
5 + 3 = -8!
0001
1100
+4
0101
+1
0000
1101
-5
0100
1010
4/29/2017
+3
+0
1111
-3
+2
0011
1011
-6
-2
+1
0000
1110
-3
-1
+0
0111
+5
+6
+7
18
Overflow Conditions
5
0111
0101
-7
1000
1001
3
0011
-2
1100
-8
1000
7
10111
Overflow
Overflow
5
0000
0101
-3
1111
1101
2
0010
-5
1011
7
0111
-8
11000
No overflow
No overflow
Overflow when carry in to sign does not equal carry out: Cn xor Cn-1
4/29/2017
Fall 2010 -- Lecture #24
19
Twos Complement
Adder/Subtractor
4/29/2017
Fall 2010 -- Lecture #24
20
Design Hierarchy
system
control
datapath
code
registers multiplexer comparator
register
state
registers
combinational
logic
logic
switching
networks
4/29/2017
Fall 2010 -- Lecture #24
21
Summary
• Use muxes to select among input
– S input bits selects 2S inputs
– Each input can be n-bits wide, indep of S
• Can implement muxes hierarchically
• ALU can be implemented using a mux
– Coupled with basic block elements
• N-bit adder-subtractor done using N 1-bit
adders with XOR gates on input
– XOR serves as conditional inverter
4/29/2017
Fall 2010 -- Lecture #24
22