Download preamp_comp_g3 cell (av_extracted view)

Layout of the Front-end
Vladimir Gromov,
P. Name
Nikhef
Amsterdam
ElectronicsTechnology
NIKHEF, Amsterdam.
GOSSIPO-3 Meeting
May 25, 2009.
Progress
Problem
Plans (May 25, 2009)
Progress:
- a new design kit has been stated at NIKHEF Virtuoso IC 6.1.3
- .sch & symbol of preamp_comp_g3 cell is checked_in NikhefWork lib
- .sch & symbol of bias_g3 is checked_in NikhefWork lib.
- pre-design of the layout of the cells
Problems:
- metallization option of V1.6.0.0DM version:
FE-I4 : 4-1-3
Mosis (20 July submit) : 3-2-3
- Triple-well NFET’s : T3 or PI options
- poly-resistor: OP P+ poly
OP RP PC poly
Plans:
- final list of the cell to be submitted / person responsible / time schedule
- layout + extraction + verification + correction + layout …..
P. Name
Nikhef
Amsterdam
ElectronicsTechnology
GOSSIPO-3 Meeting 25/05/2009
V. Gromov
2
T3 process (a quesswork)
P (BT layer)
N+ (T3 layer)
BT block
N+
N-well
P-well
P+
(IBLK layer)
connection
P. Name
Nikhef
Amsterdam
ElectronicsTechnology
GOSSIPO-3 Meeting 02/06/2009
V. Gromov
3
Progress
Problem
Plans (June 2, 2009)
Progress:
- BEOL_STACK (MA 3_2_3) has been confirmed for the submit ( Mosis, July 20)
- preliminary layout of the preamp_comp_g3 cell is checked_in NikhefWork lib (DRC is OK!)
- extraction with parasitic caps is done, analysis of the PCAPS at critical nodes is done
- ways to improve the layout have been proposed
- results of simulations with av_extracted view have been compared to those with .sch view
- specification as well as preliminary .sch view of the ingride preamp is done.
Problems:
- it is still to decide on T3 or PI options
- poly-resistor: OP P+ poly
OP RP PC poly
- extraction of the NFETTW does not work properly in preamp_comp_g3 cell,
therefore LVS does not match.
- many improvements are needed in the layout of preamp_comp_g3 cell in order
to reduce PCAPS.
Plans:
P. Name
Nikhef
Amsterdam
ElectronicsTechnology
- I assume Andre will finalize layout of the preamp_comp_g3 cell
- I will take on ingride_preamp, threshold_DAC and TDC_oscillator cells.
GOSSIPO-3 Meeting 02/06/2009
V. Gromov
4
DM (MA) version: BEOL_STACK_3_2_3
Polyimide (2.5)
from 1um to 7um over MA
Nitride (0.45)
Oxide (1.35)
LV (C4 bumpbond)
DV (wirebond)
Polyimide
MA (4.0) ALU
F1 (4.0)
L1 (resistor)
E1 (3.0) Copper
FT (4.0)
QY MIM
LY (0.46) ALU
FY (1.4)
MG (0.55) Copper
VQ (0.65)
MQ (0.55) Copper
VL (0.65)
P. Name
Nikhef
Amsterdam
ElectronicsTechnology
Kx (resistor)
Mx (x=2,3) (0.32) Copper
Vx (x=1,2) (0.35
M1 (0.29) Copper
PC wire (0.15)
PC gate
CA (0.35)
STI (0.35)
GOSSIPO-3 Meeting 02/06/2009
V. Gromov
5
Input connection layout
Test bus
E1 layer
Ctest-to-in = 1.3fF
Input pad
MA+LV layers
Cin-to-sub = 5fF
22um
P. Name
Nikhef
Amsterdam
ElectronicsTechnology
GOSSIPO-3 Meeting 02/06/2009
V. Gromov
6
Metal-to-metal capacitor
Mimcap:
E1 (3.0) Copper
Area capacitance 2.05 fF / um2
Perimeter capacitance 0.157 fF / um
E1 (3.0) Copper
FT
FT
E1 (3.0) Copper
FT
QY MIM
LY (0.46) ALU
P. Name
Nikhef
Amsterdam
ElectronicsTechnology
Vias
GOSSIPO-3 Meeting 02/06/2009
V. Gromov
7
preamp_comp_g3 cell (symbol view)
P. Name
Nikhef
Amsterdam
ElectronicsTechnology
GOSSIPO-3 Meeting 02/06/2009
Nominal voltage at the pin
Current driven in/out of the pin (both DC and AC)
V. Gromov
8
preamp_comp_g3 cell (schematic view)
A
B
C
In_preamp
P. Name
Nikhef
Amsterdam
ElectronicsTechnology
out_fb
Parasitic capacitances at these critical nodes are to be closely watched
GOSSIPO-3 Meeting 02/06/2009
V. Gromov
9
preamp_comp_g3 cell (layout view)
mimcap
28um
input pad
20um
P. Name
Nikhef
Amsterdam
ElectronicsTechnology
!!! This preliminary layout is meant to estimate the cell’s area and
check on the major problems.
!!! In the multi-wells design a lot of area is taken by clearances
between the wells.
!!! Still in-well-layout should be made much more dense by means
of sharing of diffusion regions and poly lines.
GOSSIPO-3 Meeting 02/06/2009
V. Gromov
10
preamp_comp_g3 cell (av_extracted view)
!!! ERROR: Most of the triple-well fets (nfettw) are extracted as standard nfets.
Parasitic capacitance caused by the wiring: IBM_PDK→ Query → Selected Nets PCAP / C-total
in_preamp:
out_fb:
C total=7fF (expected 3fF), Csub=5fF, Cin_preamp_test = 1.3fF (test cap), Cout_preamp = 0.8fF (feedback cap → gain↓,
expected 0fF)
consider shielding of the input pad / attached vias, space separation between input pad and the mimcap’s vias.
C total=0.14fF (very good !!!)
A:
C total=4.2fF (internal fet’s capacitance is 4fF → reduces open loop bandwidth of the preamp)
rearrange placement of the nfet’s and the pfet’s, put them as close as possible, reduce length of the connections.
B:
C total=1.6fF (internal fet’s capacitance is 2.2fF → slows down response of the comparator)
C:
C total= 1.8fF → slows down response of the comparator
P. Name
Nikhef
Amsterdam
ElectronicsTechnology
!!! Think how to arrange Vdd, gnd and bias buses for a COLOUMN of the pixel in
order to reduce parasitic coupling to the critical nodes.
!!! After running FLOATING WELLS / METALS checks, and ANTENA checks there
will be a number of tie-downs required. Those will add capacitance to the circuit.
Run these checks (together with chip_ring and bondpads with ESD protection)
before drawing final layout.
GOSSIPO-3 Meeting 02/06/2009
V. Gromov
11
Simulation with preamp_comp_g3 cell
Preamp_test_bench_23_05_09.sch
Schematic view
∆Uin=46mV
Uout_preamp = 60mV
Preamp_rise time= 10ns
Cin=1.3fF, Qin=60aC (375e-)
larger Cfb + parasitic caps
TEST BENCH :
Cpar=5.7fF
Schematic view
∆Uin=460mV
Cin=1.3fF, Qin=600aC (3750e-)
Comp_delay = 3.6ns
Av_extracted view
∆Uin=46mV
Cin=1.3fF (internal), Qin=60aC (375e-)
Av_extracted view
∆Uin=460mV
P. Name
Nikhef
Amsterdam
ElectronicsTechnology
Cin=1.3fF (internal),
Qin=6000aC (3750e-)
GOSSIPO-3 Meeting 02/06/2009
V. Gromov
parasitic caps
Cpar=5.7fF
Uout_preamp = 28mV
Preamp_rise time= 10ns
Comp_delay = 5.5ns
12
GOSSIPO-3 chip : work partitioning
Part+
Status
Work
Preamp
schematic
Design, simulation, implementation
Andre(+Vlad)
Discriminator
schematic
Design, simulation, implementation
Andre(+Vlad)
Threshold DAC/opamp
schematic
TDC oscillator
Present design
Stability- and uniformity optimization
Vlad + Sinan
Power distribution +
regulator design
schematic
Design, simulation, implementation
Chris. B
TDC & counters
schematic
Readout
check
New design
Nikhef (Ruud)
Bias blocks
???
New design
Andre(+Vlad)
I/O pads & buffers
Some of gossipo2
Copy ?
share
Analog output buffer
(voltage follower)
--
Design, simulation, implementation
Andre(+Vlad)
INGRID preamp ?
Requested
New item: specify & design
Vladimir
--
Full chip assembly & verification
Nikhef (Ruud)
Needed
Full chip assembly & verification
Andre(+Vlad)
P. Name
Nikhef Chip integration
Amsterdam
Electronics-Driver for the comp
Technology(a chain of inverters)
GOSSIPO-3 Meeting 02/06/2009
design
layout
Designers
Vladimir
ok
V. Gromov
Sinan + Vlad
13
gossipo3
VddAna
The pad color
identifies the
ESD coupling
power
in
Aout
Buf
test
Preamp
discr
Driver
bias
6 bias
Dout
VddProt
GNDAna
4x contr
THR
clk & read
Vin
P. Name
Nikhef
Amsterdam
ElectronicsTechnology
2x bias
TDC&ToT
Tout
Vout
LDO
bias
Osc_out
VddLDO
GOSSIPO-3 Meeting 02/06/2009
GNDProt
VddD
V. Gromov
14
INGRIDE preamp (inputs for design)
A:
Full reticle chip (1.4cm x 1.4cm)
Cpar = 35.2pF (huge cap) = 8.8pF/m● 2cm2 / 50μm ()
GOSSIPO-3 1.76mm x 1.76mm)
Cpar = 0.55pF = 8.8pF/m● 3.1mm2 / 50μm
Cbond_wire ≈ 1pf
B:
Cpar ≈ 2pF (reasonable cap)
Signal size (Positive Polarity): 0…20 000 electrons
4 10
4
3 10
4
p(n),
Entries
Gas gain =2000
2 10
4
Gas gain = 4000
1 10
4
Gas gain =8000
0
0
5000
4
1 10
4
1.5 10
4
2 10
Charge, electrons
P. Name
Nikhef
Amsterdam
ElectronicsTechnology
GOSSIPO-3 Meeting 02/06/2009
V. Gromov
15
Noise: on-pixel preamp
Ingride preamp
Cpar=10fF
Cpar=2pf
Id=1uA
Id=1.6mA
σnoise=70 eσnoise=700 e-
P. Name
Nikhef
Amsterdam
ElectronicsTechnology