Download Rev. PrA

700 MHz to 2800 MHz, Balanced Mixer,
LO Buffer, IF Amplifier, and RF Balun
ADL5811
Preliminary Technical Data
VPIF
32
FEATURES
RF frequency range of 700 MHz to 2800 MHz
LO frequency range of 450 MHz to 2760 MHz
IF freqeuncy range of 40 MHz to 450 MHz
Power conversion gain of 7.5dB
SSB noise figure of 11dB
Input IP3 of 24dBm over the full RF bandwidth
Input P1dB of 12 dBm over the full RF bandwidth
Typical LO drive of 0 dBm
Single-ended, 50 RF port
Single-ended or balanced LO input port
Single-supply operation: 3.6 V to 5 V
Exposed paddle 5 x 5 mm, 32-lead LFCSP
APPLICATIONS
Multi-band/ multi-standard cellular base station receivers
Wideband transmit observation receivers
Wideband radio link downconverters
Multi-mode cellular extenders and picocells
GENERAL DESCRIPTION
The ADL5811 uses a revolutionary new broadband square wave
limiting LO amplifier to achieve an unprecedented RF
bandwidth of 700 to 2800MHz. Unlike conventional
narrowband sinewave LO amplifier solutions, this permits the
LO to be applied either above or below the RF input over an
extremely wide bandwidth. Since energy storage elements are
not utilized, the DC current consumption also decreases with
decreasing LO frequency.
The ADL5811 utilizes a highly linear doubly balanced passive
mixer core along with integrated RF and LO balancing circuitry
to allow for single-ended operation. The ADL5811 incorporates
a programmable RF balun allowing for optimal performance
over a 700 to 2800 MHz RF input frequency. The balanced
passive mixer arrangement provides outstanding LO to RF and
LO to IF leakages, excellent RF to IF isolation, and excellent
intermodulation performance over the full RF bandwidth. The
NC
1
RFCT
2
IFGM
31
NC
30
IFOP
29
IFON
28
NC
27
IFGD
26
COMM
25
24 NC
23 NC
ADL5811
NC
3
22 NC
RFIN
4
21 LOIP
NC
5
20 LOIN
NC
6
19 LE
NC
7
NC
8
Serial
Port
Interface
Bias Gen
18 DATA
17 CLK
9
10
11
VLO4
COMM
VLO3
12
COMM
13
14
15
16
VLO2
COMM
VLO1
COMM
Figure 1. Functional Block Diagram
balanced mixer core also provides extremely high input
linearity allowing the device to be used in demanding wideband
applications where in-band blocking signals may otherwise
result in the degradation of dynamic range. Blocker Noise
Figure performance is comparable to narrowband passive mixer
designs. A high linearity IF buffer amp follows the passive mixer
core, to yield a typical power conversion gain of 7.5dB, and can
be utilized with a wide range of output impedances. For low
voltage applications, the ADL5811 is capable of operation at
voltages down to 3.6V with substantially reduced current. A
logic pin is provided to power down (<100uA) the circuit when
desired.
The ADL5811 is fabricated using a BiCMOS high performance
IC process. The device will be available in a 5mm x 5mm 32lead LFCSP package and operates over a −40°C to +85°C
temperature range. An evaluation board is also available.
REV. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.326.8703
© 2011 Analog Devices, Inc. All rights reserved.
ADL5811
Preliminary Technical Datasheet
ADL5811—Specifications
Table 1. VS = 5 V, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, Zo = 50, unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Unit
RF INPUT INTERFACE
Return Loss
Tunable to >20dB over a limited bandwidth
Input Impedance
Differential impedance, f = 200 MHz
DC Bias Voltage
LO INTERFACE
LO Power
Return Loss

2800
450
Externally generated
VS
-5
Low or High Side LO
MHz

200
MHz
V
0
14
50
Input Impedance
LO Frequency Range
50
40
IF Frequency Range
1
dB
700
RF Frequency Range
OUTPUT INTERFACE
Output Impedance
14
450
+10
dBm
dB

2760
MHz
DYNAMIC PERFORMANCE
Power Conversion Gain
Including 4:1 IF port transformer and PCB loss
7.6
dB
Voltage Conversion Gain
ZSOURCE = 50, Differential ZLOAD = 200
Differential
13.9
dB
10.0
dB
SSB Noise Figure
SSB Noise Figure Under-Blocking
5dBm Blocker present +/-10MHz from wanted RF
input, LO source filtered
22
dB
Input Third Order Intercept
fRF1 = 1900 MHz, fRF2 = 1901 MHz, fLO = 1697 MHz,
each RF tone at -10 dBm
25
dBm
Input Second Order Intercept
fRF1 = 1900 MHz, fRF2 = 1950 MHz, fLO = 1697 MHz,
each RF tone at -10 dBm
55
dBm
11
dBm
-40
dBm
LO to RF Input Leakage
-48
dBm
RF to IF Output Isolation
28
dB
Input 1 dB Compression Point
LO to IF Output Leakage
Unfiltered IF Output
IF/2 Spurious
-10 dBm Input Power
-65
dBc
IF/3 Spurious
-10dBm Input Power
-68
dBc
POWER INTERFACE
Supply Voltage, Vs
Quiescent Current
1
3.3
Resistor Programmable IF Current
Supply voltage must be applied from external circuit through choke inductors
REV. PrA | Page 2 of 10
5
190
5.5
V
mA
Preliminary Technical Datasheet
ADL5811
TIMING CHARACTERISTICS
Table 2. Serial Interface Timing, VCC = 5 V ± 5%
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit
20
10
10
25
25
10
20
Unit
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
t4
t5
CLK
t2
DATA
DB23 (MSB)
t3
DB22
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
t1
08817-002
t6
LE
Figure 2. Timing Diagram
REV. PrA | Page 3 of 10
ADL5811
Preliminary Technical Datasheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage, VPOS
CLK, DATA, LE
IF Output Bias
RF Input Power
LO Input Power
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
θJC (At Exposed Paddle)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Rating
5.5 V
5.5 V
6.0 V
20 dBm
13 dBm
TBD
TBD
TBD
TBD
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
REV. PrA | Page 4 of 10
Preliminary Technical Datasheet
ADL5811
1
2
3
4
5
6
7
8
TOP VIEW
24
23
22
21
20
19
18
17
NC
NC
NC
LOIP
LOIN
LE
DATA
CLK
VLO4
COMM
VLO3
COMM
VLO2
COMM
VLO1
COMM
NC = NO CONNECT
PIN 1
INDICATOR
9
10
11
12
13
14
15
16
NC
RFCT
NC
RFIN
NC
NC
NC
NC
00000-000
32
31
30
29
28
27
26
25
VPIF
IFGM
NC
IFOP
IFON
NC
IFGD
COMM
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1,3,5,6,7,8,22,23,24,27,30
2
4
9,11,13,15
10,12,14,16
17,18,19
20
21
25
26
28,29
Mnemonic
NC
RFCT
RFIN
VLO4,VLO3,VLO2,
VLO1
COMM
CLK,DATA,LE
LOIN
LOIP
COMM
IFGD
IFOP, IFON
31
32
Paddle
IFGM
VFIP
EPAD
Function
No Connect. Can be grounded.
RF Balun Center Tap (AC Ground).
RF Input. Must be grounded.
Positive Supply Voltages for LO Amplifier.
Supply Return for LO Amplifier. Must be grounded.
Serial Port Interface Control.
Ground Return for LO Input.
LO Input. Must be ac-coupled.
Ground.
Supply Return for IF Amplifier. Must be grounded.
IF Differential Open-Collector Outputs. Should be pulled-up to VCC using
external inductors.
IF Amplifier Bias Control.
Supply Voltage for IF Amplifier.
Exposed pad must be connected to ground.
REV. PrA | Page 5 of 10
ADL5811
Preliminary Technical Datasheet
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, as measured using typical circuit schematic with low-side LO unless otherwise noted.
16
10
9
14
8
SSB NOISE FIGURE (dB)
CONVERSION GAIN (dB)
12
7
6
5
4
85°C
3
10
8
6
25°C
2
‐40°C
4
‐40°C
25°C
1
2
85°C
0
500
1000
1500
2000
RF FREQUENCY (MHz)
2500
3000
0
500
1000
1500
2000
2500
3000
RF FREQUENCY (MHz)
Figure 4. Conversion Gain versus RF Frequency
Figure 7. Single-Sideband NF versus RF Frequency
30
0
‐10
‐20
20
LO‐TO‐RF LEAKAGE (dBm)
INPUT IP3 (dBm)
25
15
10
85°C
25°C
5
‐40°C
‐30
‐40
‐50
85°C
‐60
25°C
‐70
‐40°C
0
500
1000
1500
2000
2500
3000
‐80
RF FREQUENCY (MHz)
500
1000
1500
2000
RF FREQUENCY (MHz)
2500
3000
Figure 5. IIP3 versus RF Frequency
Figure 8. LO to RF Leakage versus RF Frequency
25
0
20
15
LO‐TO‐IF LEAKAGE (dBm)
INPUT P1dB (dBm)
‐10
10
85°C
25°C
5
‐40°C
‐20
‐30
‐40
‐50
85°C
25°C
‐60
0
500
1000
1500
2000
RF FREQUENCY (MHz)
2500
‐40°C
3000
‐70
500
Figure 6. IP1dB versus RF Frequency
1000
1500
2000
RF FREQUENCY (MHz)
2500
Figure 9. LO to IF Leakage versus RF Frequency
REV. PrA | Page 6 of 10
3000
Preliminary Technical Datasheet
ADL5811
REGISTER STRUCTURE
The LPF bits control the Low Pass Filter settings at the IF
output. The ability to tune the low pass filter allows some
tradeoff between Gain, Noise Figure and Input IP3 with higher
settings, 7, providing higher Input IP3 at the cost of some Gain
and Noise Figure while lower settings, 0, provide higher Gain
and lower NF at the cost of lower Input IP3. The VGS bits
control the VGS settings of the mixer core and will allow
further tuning of the device.
Figure 10 illustrates the register map of ADL5811. The ADL5811
uses only register 5. As such the Control Bits should be set to 5
in all cases. The ENBL bit, DB7 respectively, when set to 0 will
enable the part. By setting this bit to 1 the mixer will be
powered down. The CAP DAC RFB IN and Out bits are used to
tune the RF Balun. In most cases they will be tuned together
with the higher settings, 15, tuning for low frequencies and
lower settings, 0, tuning for high frequencies. There are times
where it becomes advantageous to tune the input and output of
the RF balun separately and that ability is provided for here.
RESERVED
VGS
LPF
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17
0
0
DB16
VGS2 VGS1 VGS0 LPF1 LPF0
VGS2
VGS1
VGS0
VGS SETTING
0
0
0
0
.
.
.
.
1
1
1
7
0
RFB OUT CAP DAC
DB15
DB14
DB13
CDO2 CDO1 CDO0
Figure 11 illustrates the optimum settings characterized for each
frequency band.
RESERVED
RFB IN CAP DAC
RESERVED
ENBL
DB12
DB11 DB10 DB9
DB8
DB7
0
CDI2 CDI1 CDI0
0
0
RESERVED
0
ENABLE
0
DEVICE ENABLED
1
DEVICE DISABLED
LP0
LOW PASS FILTER SETTING
0
0
0
.
.
.
CDI2
CDI1
CDI0
RF BALUN INPUT TUNING
1
1
3
0
0
0
0
.
.
.
.
1
1
1
7
CDO1
CDO0
RF BALUN OUTPUT TUNING
0
0
0
0
.
.
.
.
1
1
1
7
Figure10. ADL5811 Register Maps
REV. PrA | Page 7 of 10
0
ENBL
LP1
CDO2
CONTROL BITS
DB6 DB5 DB4 DB3 DB2
0
0
DB1
DB0
C3(1) C2(0) C1(1)
ADL5811
Preliminary Technical Datasheet
VGS
LPF
RFB OUT CAP DAC RFB IN CAP DAC
RF (MHz) DB21 DB20 DB19 DB18 DB17 DB15 DB14 DB13 DB11 DB10 DB9
VGS2 VGS1 VGS0 LPF1 LPF0 CDO2 CDO1 CDO0 CDI2 CDI1 CDI0
500
0
0
0
0
1
1
1
1
1
1
1
600
0
0
0
0
1
1
1
0
1
1
0
700
0
0
0
0
1
1
1
0
1
1
0
800
0
0
0
0
1
1
0
0
1
0
0
900
0
0
0
0
1
1
0
0
1
0
0
1000
0
0
0
0
1
1
0
0
1
0
0
1100
0
0
0
0
1
1
0
0
1
0
0
1200
0
0
0
1
0
1
0
0
1
0
0
1300
0
0
0
1
0
0
1
1
0
1
1
1400
0
0
0
1
0
0
1
1
0
1
1
1500
0
0
0
1
0
0
1
1
0
1
1
1600
0
0
0
1
0
0
1
1
0
1
1
1700
0
0
0
1
0
0
1
1
0
1
1
1800
0
0
0
1
0
0
1
1
0
1
1
1900
0
0
0
1
0
0
1
1
0
1
1
2000
0
0
0
1
0
0
1
1
0
1
1
2100
0
0
0
1
0
0
1
1
0
1
1
2200
0
0
0
1
0
0
1
1
0
1
1
2300
0
0
0
1
0
0
0
1
0
1
0
2400
0
0
0
1
0
0
0
0
0
1
0
2500
0
0
0
0
1
0
0
0
0
1
0
2600
0
0
0
0
1
0
0
0
0
1
0
2700
0
0
0
0
1
0
0
0
0
1
0
2800
0
0
0
0
1
0
0
0
0
1
0
2900
0
0
0
0
1
0
0
0
0
1
0
3000
0
0
0
0
1
0
0
0
0
1
0
Figure 11. ADL5811 Optimum Settings
REV. PrA | Page 8 of 10
Preliminary Technical Datasheet
ADL5811
EVALUATION BOARD
An evaluation board is available for the family of double balanced mixers, including the ADL5811. The standard evaluation board
schematic is presented in Figure 12. The evaluation board is fabricated on a multilayer Rogers board. Table 4 details the various
configuration options of the evaluation board.
TC4-1W+
VPOS
IFOUT
470nh
150pF
470nh
10uF
100pF
100pF
10pF
1
30
29
28
27
IFGM
NC
IFOP
IFON
NC
25
26
COMM
31
IFGD
32
VPIF
910
NC
NC
RFCT
NC
24
10k
2
23
ADL5811
NC
4
RFIN
LOIP
21
5
NC
LOIN
20
NC
LE
9
10
11
12
13
14
15
16
VPOS
10pF
10pF
10pF
Figure 12. Evaluation Board Schematic.
REV. PrA | Page 9 of 10
DATA
COMM
NC
VLO1
NC
COMM
8
Serial
Port
Interface
Bias Gen
VLO2
7
COMM
6
NC
VLO3
RFIN
3
COMM
100pf
VLO4
0.1uF
10pF
CLK
22
19
18
17
LOIN
LE
DATA
CLK
SPI
via
USB
ADL5811
Preliminary Technical Datasheet
OUTLINE DIMENSIONS
8.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
25
24
PIN 1
INDICATOR
TOP
VIEW
32 1
6.25
6.10 SQ
5.95
EXPOSED
PAD
(BOTTOMVIEW)
7.75
BSC SQ
0.75
0.60
0.50
17
16
9 8
0.25 MIN
1.00
0.85
0.80
0.80 MAX
0.65 TYP
12° MAX
SEATING
PLANE
0.35
0.30
0.25
0.80
BSC
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VLLB
Figure 13. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad (CP-32-5))
Dimensions shown in millimeters
ORDERING GUIDE
Models
ADL5811XCPZ-R71
ADL5811-EVALZ
1
Temperature
Range
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Package
Option
CP-32-5
Branding
TBD
Transport
Media Quantity
TBD, Reel
1
Z = Pb-free part.
REV. PrA | Page 10 of 10
PR09912-0-5/11(PrA)