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Squaring Function
Zehavit Trachtenberg
Ido Dinerman
Barak Cohen
Squaring Function
The squaring function is used in many applications
such as the Viterbi alg. (error correction code),
VQ alg. (image data compression, speech and
writing recognition) and calculating Euclidean
squared distance estimation.
Fast implementation for RT purposes is needed,
two of which will be explored in this work:
1. Digital implementation – compensating
algorithm by Ming-Hwa Sheu and Su-Hon Lin.
2. Analog implementation.
Project Goals
 Function
implementation – Analog (Spice)
 Function implementation – Digital (VHDL)
 Implementation of function for practical
use (Pythagoras Theorem).
DIGITAL
Digital Implementation
 The
digital implementation is based on the
approximate squaring function.
 Input: n-bit binary data
A = Σ 2i*ai
i=0..n-1
Output: 2n-bit binary number
R = Σ 2m*rmn ≈ A2 m=0..2n-1
Algorithm

The output expression of the exact
squaring function is:
(for a 4 bit number)
A² = (a3a2a1a0)²
= 26(a3+a3a2) + 25a3a1+
24(a2+a3a0+a2a1)+23a2a0+
22(a1a0+a1)+20a0
Algorithm cont.
Step 1: The approximate result R is equal to the
pure terms
R = 26a3+24a2+22a1+20a0
Step 2: Select the closest composite terms for
compensation (26a3a2 , 24a2a1, 22a1a0):
R=26(a3+a3a2)+24(a2+a2a1)+
22(a1+a1a0)+20a0
=27a3a2+26a3a2+25a2a1+24a2a1+23a1a0
+22a1a0+20a0
Algorithm cont.
Step 3: choose the second closest
composite terms for compensation.
do the same as step 2 (terms 25a3a1,
23a2a0) The result is:
R= 27a3a2+26a3(a2Ua1)
+25(a3+a2)a1+24a2(a1Ua0)
+23(a2+a1)a0+22a1a0+20a0
Algorithm cont.
Step 4: the approximation:
Add the remaining term (24a3a0) to the sum
with the OR operator:
R=27a3a2+26a3(a2Ua1)
+25(a3+a2)a1+24a2(a1Ua0)Ua3a0
+23(a2+a1)a0+22a1a0+20a0
Algorithm result
r47 = a3a2
r45 = a3a2a1Ua3a2a1
r43 = a2a1a0Ua2a1a0
r41 = 0
r46
r44
r42
r40
= a3a2Ua3a1
=a2a1Ua2a0Ua3a0
= a1a0
= a0
Algorithm cont.
By induction:
rni-1 = an-1an-2
rni-2 = an-1an-2Uan-1an-3
rni-3 = an-1 (rn-1i-3) U an-1an-2an-3
rni-4 = (rn-1i-4)Uan-1an-4
rni-n = (rn-1i-n)Uan-1a0
rni-n-1 = (rn-1i-n-1)
rn0 = (rn-10)
Algorithm error


Error =
(A² - R) /A²*100%
the error increases with
the length of the number.
i.e. for 4 bits the error is
9.47% and for 10 bits the
error is 18.19%
Average error : 4 bits
1.04% and 10 bits 4.21%
100
80
60
16 bit
40
4 bit
20
16 bit
0
31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
Implementation
 VHDL
simulation of the function.
 implementation in the transistor level
using CMOS transistors.
 Place and route for the circuit.
 size, power and speed analysis.
SPICE Implementation
SPICE Simulation
Simulation Results
I
LSB N
P
U
T
MSB
LSB
O
U
T
P
U
T
MSB
Propagation Delay
 Propagation




Delay :
Nand2: Tpd = 5.1 ns
Nand3: Tpd = 6.2ns
Nor2: Tpd = 4.4ns
Buffer: Tpd = 6.6 ns
 The
propagation delay for the critical path
(the one for R2 or R7) is a nor2 gate and
a buffer, thus Tpd is 11ns
Layout (Logic)
Layout (chip)
out8
out7
out6
out1
out5
Vcc
out4
in1
Gnd
in2
out3
in3
in4
out2
LVS Result
VHDL Implementation
 The
digital model was implemented using
VHDL structural architecture similar to the
spice implementation.
 Propagation delay times were calculated
using simulations of scmos library logical
gates.
VHDL simulation results
VHDL simulation results cont
The errors in the algorithm occurred in a = 13
and in a = 15
Expected results :
for a = 13 r = 169 simulation result = 153
for a = 15 r = 225 simulation result = 209
Error Correction
Different methods for producing an errorfree Digital Squaring Function:
• Implementing the shown algorithm
without using approximation.
• Correcting 2 error outputs using an Error
Correction Unit.
Straightforward Calculation
r47 = a3a2+[a3(a2+a1)]{[(a3+a2)a1][a2(a1+a0)a3a2]}
r46 ={[a3(a2+a1)] + [(a3+ a2)a1][a2(a1+a0)a3a0]}
r45 =[(a3+ a2)a1] + [a2(a1+a0)a3a0]
r44 = a2(a1+a0) + a3a0
r43 = a1a0+ a2a0
r42 = a1a0
r41 = 0
r40 = a0
Straightforward Algorithm
cont.
Estimated number of transistors per each output
bit:
r47 = 52
r46 = 44
r45 = 32
r44 = 18
r43 = 6
r42 = 4
r41 = 0
r40 = 0
input inverters = 8
Buffers ~36
Total # transistors ~200
Important : the calculated number does not contain transistors in buffers.
Straightforward Algorithm
cont.
Calculating the Propagation Delay:
# of levels in longest path (R7) = 5
Pd for a NAND2 gate = 5.1ns
Pd for input inverter = 3ns
Total Pd (worst case) = 28.5ns
Error Correction Unit
Designing an error correction unit for
squaring a 4-bit number.
The following implementation deals with 2
errors:
Err1: 132 = 153…  132 = 169
Err2: 152 = 209…  152 = 225
Error Correction Unit
INPUT:
approximated
result
OUTPUT:
correct
result
Simulation Configuration
Error Correction Output
correct
output!
LSB I
N
P
U
MSB T
LSB
O
U
T
P
U
T
MSB
Error Correction –Pros & Cons
Pros:
•
It’s correct!
Cons:
•
Area usage
•
Resources & Cost – 120 transistors in
correction unit.
•
Propagation – requires synchronization in
order to avoid hazards (at Squaring Function
output), considerable increase in propagation
delay
•
Not a generic solution
Comparing Error Correction
Methods
Compensated
implementation
Error
Correction Unit
Straightforward
Implementation
# of
transistors
104
104 + 120
~200
Pd (worst
case)
13.2 ns
Extra synch.
Unit required
28.5 ns
Power
3.02*10-16*f
3.02*10-16*f+
3.98*10-16*f
~6*10-16*f
Area
1.72*10-8m2
1.72*10-8m2
+1.7*10-8m2
~2.45*10-8m2
ANALOG
Analog implementation


Consider the following
arrangement of CMOS
transistors.
M1, M2 in saturation.
The equation of transistors in
saturation is:
Id=K(Vgs-Vt)²
in our circuit:
I1=K(Va-Vt)²
I2=K(Vb-Vt)²
Vb = V2 – Va
Analog implementation cntd.
combining the three equations we will receive
the following:
difference of output currents:
I1 – I2 = K(V2-2Vt)(Va-Vb)
sum of output currents:
I1 + I2 = ½K(V2-2Vt)²+(I1– I2) ²/2K(V2-2Vt)²
Analog implementation cntd.
In order to provide a
stable V2 voltage
source we will use a
current controlled
circuit.
I0 = 1/4 K(V2-2Vt) ²
Analog implementation cntd.
By connecting the
drain and the
source of M1 we
get our new circuit.
Our previous
equations still hold.
We consider Iin as
an input. we get:
Iin = I1-I2
Analog implementation cntd.
We copy I1 using a current
mirror, hence we get:
Iout = I1+I2
Now, we substitute Iin and
Iout in our previous result:
I1 + I2 = ½K(V2-2Vt)²+
(I1– I2) ²/2K(V2-2Vt)²
We get:
Iin= ½K(V2-2Vt)²+
(Iout) ²/2K(V2-2Vt)²
Analog implementation cntd.
Remember that V2 is controlled by the control current
I0 = 1/4 K(V2-2Vt) ²
substituting this in the previous expression we finally get:
Iout = 2I0+ Iin2 / 8I0
We can eliminate the offset current 2I0 by subtracting it from the
output. We do so by copying I0 twice and subtracting it from I0 . We
finally get:
Iout = Iin2 / 8I0
In order to keep all the devices in the circuit in ON state we have to
maintain the following:
|Iin| < 4I0
The final squaring circuit:
Simulation results
Dc analysis: sweep of input current -4*I0  4*I0
Control current of 175uA gives the best results:
expected
output
Max absolute Error of 8uA
Approximated Error in percentage: ~0.75%
Simulation results
Square of sin function:
expected
output
BW of 10MHz
For each frequency the input is sin(wt). The expected output – sin2(wt) is presented as well as the output of the circuit.
10MHz
100MHz
1GHz
10GHZ
Analog summary
Area: 8 transistors (Very small)
Band Width: 10MHz
Input Current Range :
-700uA  700uA
Absolute Error: 8uA (accuracy error more
effective than enviromental errors – noise)
Error in percentage: ~0.75%
hence the device can handle a range of
2*(700/8)=180 values.
 Constant power dissipation (can be reduced
when the device is not in use by adding more
hardware)



Analog Square Root
 The
equation of
transistors in
saturation is:
Id  K(Vgs - Vt)²
 By
solving for Vgs we
get:
Vgs 
Id
 Vt
K
Analog Square Root
output
expected
C = sqrt(A2+B2)
We combine all the results so far in order to implement Pythagoras
Theorem and find an Euclidian distance:
Results
Sqrt(A2+B2)
A2+B2
Input
expected
output
Pythagoras 2nd try
Results
Sqrt(A2+B2)
A2+B2
Input
expected
output
Bibliography
(1)
Fast Compensative Design Approach for
the Approximate Squaring Function Ming-Hwa Sheu and Su-Hon Lin,
IEEE Journal of Solid-State Circuits, Vol.37, No.1, Jan 2002
(2)
“A Class of Analog CMOS Circuits Based
on the Square-Law Characteristic of an
MOS Transistor in Saturation” by Klass
Blut and Hans Wallinga,
IEEE Journal of Solid-State Circuits, Vol.SC-22, No.3, June 1987
THE END