Download review for elec 105 midterm exam #1 (fall 2001)

ELEC 350
Electronics I
Fall 2005
Review Topics for Final Exam
 The following is a list of topics that could appear in one form or another on the exam. Not all
of these topics will be covered, and it is possible that an exam problem could cover a detail not
specifically listed here. However, this list has been made as comprehensive as possible.
Remember to review the topics listed on the previous sheets since the final exam is cumulative.
Qualitative understanding of operation of enhancement-mode MOSFET
- threshold voltage Vt
- effect of increasing vGS (charge carriers flood channel as vGS rises above Vt)
- effect of increasing drain-source voltage vDS (channel bottom tilts as vDS rises)
- directions and polarities of important currents and voltages (e.g, iD and vDS)
- depletion region around drain
- formation of channel along substrate directly under gate
- pinchoff condition (present when FET is in saturation, or constant-current, region)
- electron and hole mobilities; typical values are n = 450 cm/Vs and p = 200 cm/Vs
- capacitance of gate per unit area, Cox = ox / tox (ox, tox = permittivity and thickness of
oxide layer); typical values are around 1-10 fF/m2
- process conductance parameter kn’ = nCox or kp’ = pCox; unit is A/V2
MOSFET i-v characteristic (iD vs. vDS for selected values of vGS)
- cut-off state (vGS < Vt): iD = 0
- saturation region, or constant-current region (CCR), (vDS > vGS – Vt): iD = K(vGS – Vt)2
- triode region (vDS < vGS – Vt): iD = K[2(vGS – Vt)vDS − vDS2]
n-channel vs. p-channel MOSFETs (NMOS and PMOS)
- vGS, vDS, and Vt are all negative for enhancement-mode PMOS
- iD is positive for both types (Sedra and Smith’s convention)
- i-v characteristics of NMOS and PMOS have voltages of opposite sign
MOSFET circuit symbols
- n-channel vs. p-channel
- simpler symbol when substrate is tied to source internally
- directions of arrows
CMOS digital logic gates
- use no resistors
- negligible drain current once equilibrium is established after logical state change
- MOSFETs are either in cutoff (“off”) or triode region (vDS ≈ 0) in all logical states
General analysis techniques for MOSFET circuits
- determination of region of operation (cutoff, saturation, or triode)
- vDS for n-channel MOSFETs will always be zero or positive (negative for PMOS)
- graphical analysis techniques (load lines) can be applied
- resolution of sign ambiguities when quadratic formula is required due to square-law
dependence of iD on vGS
Distinction between bias, signal, and total voltages and currents
- signals are usually time-varying, but don’t have to be
- signals contain information (audio, video, data, sensor outputs, etc.)
- bias conditions (DC levels) define the “Q-point”
- total voltage or current is sum of bias and signal components (superposition)
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Concept of biasing and why it’s necessary
Convention used to represent bias, signal, and total quantities (Sedra and Smith)
- total = lower case variable/upper case subscript
- bias (DC) = upper case variable/upper case subscript
- signal (general time-varying) = lower case variable/lower case subscript
Biasing MOSFET circuits
- designing for quiescent output voltage, drain current, and/or voltage drop across
source resistor
- the parameters K and Vt have strong temperature dependence and device variation
- parameter-independent biasing (source degeneration)
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o must satisfy I D  K n VGS  Vt  and VGS  VG  I D RS
o square-law behavior leads to solution of quadratic equation
o Which of the two solutions to the quadratic equation is the physical solution?
V  Vt
1
1
o exact solution: I D  G


1  4KRS VG  Vt 
2
RS
2KRS 2KRS2
1
o practical solution: I D RD  I D RS  VDD and VG  I D RS  Vt  I D K n
3
RB
- establishment of gate bias voltage simplified because IG = 0: VG  VDD
R A  RB
- gate biasing resistors should be in the M range
- enhancement-mode MOSFETs require positive gate bias voltage and VGS > VTR
- depletion-mode MOSFETs can have negative, positive, or zero gate bias voltage, but
still require VGS > Vt (Vt is negative); zero gate voltage bias is most common
- swing range of vD to avoid cut-off and triode regions
DC blocking capacitors
- act as open circuits at DC
- isolate biasing from effects of source and/or load
General small-signal modeling
- definition of “incremental signal” (fluctuations are a small fraction of bias level)
- separation of bias considerations (quiescent levels; output voltage swing range) from
small-signal considerations (gain, input and output resistance)
- replacement of DC voltage sources with short circuits (because voltage across a DC
voltage source can’t change)
- replacement of DC current sources with open circuits (because current through a DC
current source can’t change)
- replacement of large capacitors with short circuits (if capacitive reactance is
insignificant at operating frequency)
- replacement of large inductors with open circuits (if inductive reactance is very large
at operating frequency)
- DC voltage sources are typically bypassed at AC (i.e., at signal frequency) using
capacitors to ensure that the source acts as an AC ground.
- small-signal models of FETs and BJTs are only valid when device operates in the
constant-current region (saturation for MOSFETs, active for BJTs)
- small-signal models are not valid in cut-off or triode region (FETs)/saturation (BJTs)
- derivation of small-signal voltage gain vo/vin, input resistance, and output resistance
(use test source for latter)
- simplifications in gain/resistance expressions when one term is much greater/smaller
than another term
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Small-signal modeling of MOSFET circuits
- gate-source path modeled as an open circuit
- small-signal transconductance gm
i
o basic definition: g m  D
vGS v V
GS
GS
o equivalent formulas: g m  2KVOV  2K VGS  Vt  
2I D
 2 KI D ,
VGS  Vt
W
W 1
  n or p C ox
where K  k n or p 
L 2
L
o derivation of these formulas
- incremental drain-source resistance ro
o represents non-zero slope of iD-vDS characteristic in the saturation region
o typically 20-100 k for MOSFETs
o as low as 400-500  for GaAsFETs (and others?)
V
o ro  A , where VA = Early voltage
ID
- effect of source degeneration resistor (RS) on gain
- common-source (CS), common-gate (CG), and common-drain (CD) amplifiers
Internal structure of bipolar junction transistor (BJT)
- npn: thin p-type base sandwiched between n-type emitter and collector
- pnp: opposite of npn
Qualitative understanding of operation of BJT
- turn-on voltage (VD0) of base-emitter junction (approx. 0.7 V for Si)
- effect of changing base current iB
- effect of changing collector-emitter voltage vCE
- directions and polarities of important currents and voltages (iB, iC, iE, vBE, vCE)
- thin base region required to allow electrons (npn) or holes (pnp) to flow from emitter
to collector
- emitter more heavily doped than base – allows base to fill with minority carriers when
base current flows
- base-emitter junction is forward biased if vBE is at turn-on voltage (VD0)
- i-v characteristic of B-E junction is the same as that of a pn-junction diode
- collector-base junction is usually reverse biased (produces depletion region) or lightly
forward biased
- collector current related to base current by iC = FiB in the active region
- F = forward DC current gain (values are typically 20-300, but vary among BJT
types, even among individual units of a given type within the same manufacturing
batch)
BJT i-v characteristic (iC vs. vCE for selected values of iB)
- cut-off region (vBE < VD0, iB = 0, and iC = 0)
- active (constant-current) region (iC = FiB)
- saturation region (vCE ≈ 0.2-0.3 V and iC < FiB, but iC is nonzero)
npn vs. pnp BJTs
- circuit symbols (arrow indicates emitter; arrow of npn is “not pointing in”)
- vBE, and vCE of pnp BJTs have negative values in normal operation
- iB and iC flow out of base and collector terminals of pnp BJTs
- i-v characteristics of npn and pnp BJTs have voltages and currents of opposite sign
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General analysis techniques for BJT circuits
- determination of region of operation (cutoff, active, or saturation)
- vCE (for npn BJTs) will always be positive (negative for pnp)
- graphical analysis techniques (load lines) can be applied
- vBE = 0.7 V (for npn) in the active and saturation regions
- in active region, iC = FiB
- in saturation region, vCE = vCE|sat ≈ 0.2-0.3 V and iC < FiB
Inverter circuits
- can be used as logical NOT gates
- transfer characteristic (vo vs. vin) has negative slope (or zero slope in some regions)
- MOSFET version is also called a common-source amplifier
- MOSFET inverter with resistor load has nonlinear transfer characteristic in saturation
and triode regions (because MOSFETs are “square-law” devices)
- MOSFET inverter with MOSFET load is linear when both devices are in saturation
- CMOS inverter uses no resistors and has negligible drain current once equilibrium
has been established after a logical state change
- BJT version is also called a common-emitter amplifier
- BJT inverter has a linear transfer characteristic in active region
Relevant course material:
HW:
Labs:
Textbook:
#8-9
#12-13
Sections 4.2.1-4.2.4, 4.3, 4.4, 4.5, 4.6.1-4.6.6, 4.7
Sections 5.1-5.3 (highlights only), 5.4
Lecture notes: no new notes
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