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Using Transmission Lines
From our earlier discussions
 Effective length of electrical feature
Measure of how quickly that feature appears throughout the system

Our distinction between lumped and distributed
Based upon the rise (or fall) time of the signal
l
Tr
D
We should consider using transmission line techniques
Based upon how quickly signal is appearing throughout system
Specifically when round trip delay of signal propagating down line
Close to or greater than signal frequency
Tline > Trise
That is when signal(s) of interest not appearing
At all parts of circuit simultaneously
Compounding problem
Reflections of original signal
Delayed by the line propagation time
Will increase settling time relative to signal frequency
High Speed Conduction
Several configurations used for high speed paths
Involve
 Discrete wiring
 Printed wiring
 Dielectric material
Now dealing with electromagnetic fields
Goal is design structure with
 Controlled impedance
 Reduced crosstalk
 Reduced EMI
Bogatin - 205
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Transmission line structures
Comprise
 Conductive traces
Attached to or buried in dielectric material
Usually FR4 PCB material
 One or more reference planes
Usually copper
Geometries
Structure cross sections given as
Graham and Johnson page 140
Parallel Lines
Twisted Pair
Co-axial Line
Reference Planes
Image Line
Micro Strip Line
Twisted
Shielded Pair
Strip Line
Reference plane
Ground
Ground and power



Image line
 Reference plane – ground
Reduces self inductance around loop
Micro Strip Line
 Most commonly used
 Usually routed on outer layer
 Single reference plane less isolation
 Can mount all active components on top side of board
 Can radiate
 Is dispersive
Signals at different frequencies travel at different speeds
Strip Line
 Most commonly used
 No dispersion
 Excellent isolation between traces
 Harder to fab than strip line
 Narrows strip line widths
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Model
Now consider modeling as distributed system
Seely page 223
Assumptions
1. Transmission line is two parallel wires
2. Can characterize by
 Series resistance
Expresses loss along path
 Shunt conductance
Expresses leakage between lines
 Series inductance
 Shunt capacitance
Note inductance and capacitance impedances
Function of frequency
3. All measurements are per unit length
Let's look at a distributed model
Can model incremental section of transmission line as two port device
v
i
+
+
+
v
x
x
x
v
v
i
i
-
i + i
i
v + v
x
distance co-ordinate measured from one end of the line
increment of x co-ordinate
potential at point x of line
increment of potential over distance x
current in conductor at point x
increment of current between wires
due to both conductive and capacitance effects in interval x
- 3 of 18 -
For infinite transmission line
Voltage at any point in ideal transmission line
Perfectly delayed copy of input signal
Delayed by the propagation delay of the line
This is the inverse of the propagation or transmission velocity
Electrically we now have
Δv
L dx
R dx
v v
L dx
v + Δv
R dx
G dx
C dx
G dx
C dx
Δi
In our model
v i -
arises from drops across the series resistance and inductance
arises from leakage through shunt capacitance and conductance
From above we can now write the following equations
v x  x   v x   v x   R( x )xi x   jL( x )xi x 
i x  x   i x   i x   G( x )xv x   jC( x )xv x 
Divide by x and let dx -> 0
d v x 
  Ri x   j Li x 
dx
d i x 
 G v x   j C v x 
dx
Solving these for separate equations in v and i
d 2 v x 
  R  j L G  j C  v x   0
dx 2
d 2 i x 
  R  j L G  j C i x   0
dx 2
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Solutions now become
v x   v1e  x  v 2 e  x
i x   i1e  x  i 2 e  x
R  jL G  jC 
 Called propagation constant
v(x) expresses the voltage at any point along the transmission line
Both current and voltage equations
 Phasors
 Reflect signals as function of x along signal path
With a little bit of math
Can write characteristic impedance of transmission line as
V
R  jL
Z0  
I
G  jC
In limit as ω→∞
Z0 
L
C
Giving a lossless transmission line
Lossless Transmission Line
If we assume a lossless transmission line
From impedance point of view
G will often be very small
See Graham and Johnson page 140 for geometries
Let R = G = 0
Transmission line will be purely reactive
Characteristic impedance once again becomes
Z0 
L
C
Propagation Velocity - inverse of propagation delay (delay per inch)
Recall that delay depends upon dielectric constant of surrounding medium
- 5 of 18 -
Propagation delay in ps/in given as
 p  LC
Propagation velocity in in/ps given as
p 
1
LC
Based upon assumption G=R=0 signal attenuation given as
 0
Transmission line now perfect delay line
Vin
t=length*p
Vin
t=0
With
 p  LC
Finite Transmission Line
Consider following circuit
From Thevenin perspective of components
Looking back into driver
Have impedance ZS
Looking into receiver
Have impedance ZL
We now have following model
-
I0
ZS
+
+
VS
(V0)-
I0
+
+
ZL
(V0)+
These are phasor voltages
X=0
X=L
- 6 of 18 -
From impedance perspective we have from
Source to path to destination
ZS
source
Z0
signal path
ZL
destination
Since system is linear
Using superposition of forward and backward signals
Along path have incident and reflected waves
V V  V0
0
V is a phasor voltage at any point along the line →|V|∟Ф
I I  I0
0
Note - the current has changed direction the voltage has not
Voltage still remains potential between two conductors
From Thevenin and Ohm
We can express the characteristic impedance at any point along the line as
V0  V0
Z0   
I0  I0
Remember the voltages and currents are of the form
vx   v1e x  v2e x
ix   i1e x  i2e x
- 7 of 18 -
If we let Vs be a sinusoid with frequency 
We then have V0 of forms
V0 sin t   
V0 sin t   
From Ohm
Ratio of V/I at load end must equal ZL
Using superposition of incident and reflected waves
V at any point is –
V  V0  V0
I at any point is
I  I 0  I 0
Thus we get
V V0  V0
 
 ZL
I
I 0  I 0
V0  V0
ZL  
V0 V0

Z0 Z0
With a little bit of math we get

V0  ZL  Z0 


V0  ZL  Z0 
 Gamma
V0 reflected wave
V  incident wave
0
(V0)- =Γ(V0)+
+
VS
- 8 of 18 -
Z0
Z0
(V0)+
ZL
Rewriting we get
 Z  Z0 

V0  V0  L
 ZL  Z0 
We call  the reflection coefficient
Observe
V0  V0
Gives measure of percent of incident signal reflected back
Boundary Conditions

High impedance device
Load appears as open


Open Line ZL =   V0  V0


Z L  Z0
1
Z L  Z0
Low impedance device
Load appears as short


Shorted Line ZL = 0  V0  V0


Matched Line ZL = Z0


Z L  Z0
 1
Z L  Z0
Z L  Z0
0
Z L  Z0
In general
||1
- 9 of 18 -
Transient Input
Let's now consider a step input into a simple system
Looking from source into signal path
Zs
V1
Vs
Zo
Analysis
Initial voltage divider between source impedance and line
V Z
V s 0
1 Zs  Z0
Voltage travels down transmission line
Reflects when hits load
Z0
V1  loadV1
ZL
Reflected wave travels back towards source

2

load 1
V  source 
Z0
V
That is - we now have
 Z S  Z0   Z L  Z0  

V 2  Z S  Z0   Z L  Z0  V 1

Reflected wave re-reflects when it hits source
Reflections die out because  < 1
Let's now see what this means in the real-world
- 10 of 18 -
ZS
Terminations
Graham and Johnson pages 169-170
Unterminated
We consider a line to be unterminated
When neither the source nor the load impedance
Matches the characteristic impedance of the line
Observe once again
Even with LSI and VLSI circuits
We have many boundaries where we can have such a mismatch
Low Source Impedance - TTL/ ECL Drivers
These devices have low source impedance
Zs << Zo, and ZL = 
Signal





Leaves source
Travels down path
Reflects off load
Returns down path
Reflects off source
 ZS Z0   ZL Z0  

V
 ZS  Z0   ZL  Z0  1
 
V2
Gives reflection coefficient  approaching -1
With a reflection coefficient of -1
 Successive reflections are of opposite sign
 Requires 2 round trips (4 traversals)
Before successive signals have same polarity
 Response to input signal oscillates as it damps out
  V 
After single round trip V 2
1
1 Round Trip delay
- 11 of 18 -
If rise time shorter than round trip delay
Tline > Trise
Have a distributed rather than lumped model
Overshoot will be evident in output signal
Overshoot can cause excessive current to flow in
 Input protection diodes in most TTL / CMOS gates
 Current returns through chip's ground pin
Causes ground bounce between
Internal ground reference
Ground plane
In extreme cases
Can damage input protection circuitry
High Source Impedance - CMOS Drivers
These devices have high source impedance
Zs >> Zo, and ZL = 
 ZS Z0   ZL Z0  

V
 ZS  Z0   ZL  Z0  1
 
V2
Gives  approaching +1
With a reflection coefficient of 1
 Successive reflections are of the same sign
 Response to input signal builds up monotonically from successive
reflections
1 Round Trip delay
- 12 of 18 -
Parallel Termination - End Terminated
When terminating resistance placed at receiving end of transmission line
Called parallel termination
Graham and Johnson 220-230
To eliminate reflections
Value must match effective impedance of line
Goal

ZS = 0, ZL = Z0
With parallel termination we have basic case
 ZS Z0   ZL Z0  

V
 ZS  Z0   ZL  Z0  1
 
V2




With ZL = Z0 we eliminate the first reflection at destination
Thus no reflection off source
Full amplitude input waveform dwon line
Reflections damped by terminating resistor
Non-zero static power dissipation
0
VS
+
C
Z0
VS
Implementation
We’ll look at two schemes
 Biased termination
 Split termination
- 13 of 18 -
ZL
Biased Terminations
With biased termination
Goal is to ensure device spends half time in each state
No DC power dissipation
Give voltage across cap as
V OH V OL V

VC
2
2
From which we get a power dissipation of
Z0
R0 = Z 0
 
2
ΔV 2
V 

2

P R0 
Z0
4Z0
DC Balanced
Using following model
Z0
VS +
Z0
Z0
Z0
C0
C0
The time constant rise and fall time for the signals becomes
  2 Z0C
Note that C is going to the parallel combination of C0 and parasitics
- 14 of 18 -
C0
Split Termination
Common implementation
Implement termination as split resistor shown here
VCC
Z0
R1
Z0= R1|| R2
R2
Split
Termination
parasitic
Looking into output we compute
Rth 
VCC
R1R2
 Z0
R1  R2
R1
R2
R2
Vth  Vcc
R1  R2
For the split termination we get a power dissipation of
P R0 
 V 
2
2 Z0
Looking into load with R1 and R2 = 2 Z0
The time constant rise and fall time for the signals becomes
VS +
R1
R2
C
  Z0C
In this case C is the parasitic capacitance
- 15 of 18 -
R1
R2
C
Often cannot match line impedance exactly
Resulting reflections affect receiver's noise margin
May be acceptable
When selecting R1 and R2 we must adhere tot he following constraints
1. The parallel combination of the two resistors must equal Z0
2. We must not exceed IOHmax or IOLmax
V CC V OH V OH V SS

 IOH max
R1
R2
V CC V OL V OL V SS

IOL max
R1
R2
IOH R1
Another commonly used scheme for line termination is called
Source terminated
Termination
Placed on driving rather than receiving end
Series rather than parallel
Rs
C
Goal
RS + driver output impedance = Z0,
RL = 
- 16 of 18 -
Idrive
R2
VCC
IOL R1
R2
Series Termination - Source Terminated
VCC
Idrive
With series termination we get
 Half amplitude input waveform
 Reflections at load creates full magnitude
 Reflections damped at source
 No Static power dissipation
 Half the rise time of parallel termination
Load 


ZL  Z0
 1
ZL  Z0 ZL  
With reflection coefficient of +1 off load
Reflected signal adds to incident


ZS  Z0
0
Source 
ZS  Z0 Rs  Z 0
Therefore the signal reflects off the destination
With no second reflection off source
Outgoing signal + the reflected signal
Bring signal to full strength
0.5 Vs
Z0
+
Vs
0.5 Vs
Z0
Select Rs – the termination
Z0 - ZOH < Rs < ZO - ZOL
ZOH and ZOL values for specific part
- 17 of 18 -
From the data sheets for the individual logic families
We compute the output impedances as follows
ZOutput 
ZOL 
V out
thus for HCI
I out
V OL 0.15 vDC

37  typical
4.0 mA
IOL
ZOL = 37 typ - 83 max
ZOH = 45 typ - 165 max
Strengths
Has low power consumption between transients
Can be implemented with one resistor
Weaknesses
Degrades edge rate more per unit of capacitive load
Requires transmission round trip delay to achieve full step level
Diode Clamping
Diode turns on at 0.6 to 1 V limiting reflections
May not respond fast enough
Should look familiar as IC input circuit
Vss
Z0
VS
+
Z0
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