Download Instruction SET Architecture - Department of Physics, Computer

CPEN 315 - Digital System Design
Chapter 10 – Instruction SET
Architecture (ISA)
© Logic and Computer Design Fundamentals, 4rd Ed., Mano
Prentice Hall
© Computer Organization & Design,
The Hardware/Software Interface - Third Edition
Computer Organization
Application
Operating
System
Compiler
Firmware
Instr. Set Proc. I/O system
CPSC 414
Datapath & Control
Digital Design
Circuit Design
Layout
 Coordination of many levels of abstraction
 Under a rapidly changing set of forces
Forces on computer architecture
Technology
(a = SF/m)
Programming
Languages
Applications
Computer
Architecture
Operating
Systems
cleverness
History
The big picture

Since 1946 all computers have had 5 components
Processor
Control
‘brain’
Datapath
‘brawn’
Memory
ROM
DRAM
SRAM
Cache
Input
keyboard
mouse
disk
Output
display
printer
What is the significance of Computer
Architecture?


It impacts every other aspect of computer/electrical
engineering and computer science.
It’s exciting! Microprocessor performance growth
“unmatched by other industries” [John Crawford, Intel
fellow]
Processor speed has doubled every 18 months (1982-1996)
— Cars would travel at 44,000 mph and get 16,000 miles/gal.
— Air travel: L.A. to N.Y. in 22 seconds.
What is the significance of Computer
Architecture?
Itanium
(~ 2 billion
Transistors)
Computer architecture
is becoming more
important as computer
technology continues
to advance.
Single-Electron
Transistor
Why study Computer Architecture
covered in CPEN315 CPSC330 and CPEN414?


If you want to call yourself a “computer scientist”
Programmers and computer scientists who seek to
build competitive versions of compilers, operating
systems, databases and even applications will need
to increase their knowledge of computer architecture
and organization:
- interface between the software and hardware
- performance of a program
- hardware techniques that affect performance
What is “Computer Architecture”?
Computer Architecture =
Instruction Set Architecture +
Machine Organization + …..
The Instruction Set: a Critical Interface
software
instruction set
hardware
Instruction Set (IS) Architecture - continued

A very important abstraction
• interface between hardware and low-level software
• standardizes instructions, machine language bit
patterns etc. IS includes anything programmers
need to know to make machines language program
work correctly including instructions, registers,
memory access, I/O devices, etc.

Instruction set architectures:
• 80x86/Pentium/K6, DEC Alpha, MIPS, SPARC
(Scalable Processor Architecture), HP workstations
From a high-level language to the language
of the hardware
temp = v[k];
High Level Language
Program
v[k] = v[k+1];
v[k+1] = temp;
Compiler
lw $15,
lw $16,
sw $16,
sw $15,
Assembly Language
Program
Assembler
Machine Language
Program
0000
1010
1100
0101
1001
1111
0110
1000
1100
0101
1010
0000
0($2)
4($2)
0($2)
4($2)
0110
1000
1111
1001
1010
0000
0101
1100
1111
1001
1000
0110
0101
1100
0000
1010
1000
0110
1001
1111
Machine Interpretation
Control Signal
Specification
°
°
ALUOP[0:3] <= InstReg[9:11] & MASK
RISC




Characteristics:
Uniform instruction format, with the opcode in the
same bit positions in every instruction, demanding
less decoding.
Identical general purpose registers, allowing any
register to be used in any context, simplifying
compiler design (although normally separate
floating point registers)
Simple addressing modes. Complex addressing
performed via sequences of arithmetic and/or loadstore operations
RISC Instruction Format
R-type:
add $t3, $t2, $t6

I-type:
addi $t2, $t3, 6

based or indexed addressing:
lw $t2, 4($t0)
-Load word at RAM address ($t0+4) into register $t2
-"4" gives offset from address in register $t0
RISC Instruction Format - continued
based or indexed addressing:
sw $t2, -12($t0)
- store word in register $t2 into RAM at address ($t0 12)
- negative offsets are fine
Jumps
j target # unconditional jump to program label target
jr $t3 # jump to address contained in $t3 ("jump
register")

Simple datapath with control unit
0
M
u
x
Add
ALU
Add result
4
op
Control
rs
Instruction [25–21]
PC
Read
address
Instruction [20–16]
rt
Instruction
[31–0]
Instruction
memory
0
M
u
Instruction
[15–11]
x
rd
1
Read
register 1
Read
register 2
Write
register
Write
data
Instruction [15–0]
Shift
left 2
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Instruction [31–26]
16
1
Read
data 1
Zero
Read
data 2
Registers
Sign
extend
Instruction [5–0]
0
M
u
x
1
ALU ALU
result
Address
Read
data
Data
Write memory
data
32
ALU
control
1
M
u
x
0
Mapping Control to Hardware
Let’s try Opcode = 000000
What type of instruction format?
PLA structure
Datapath & Control
phases of R-type instruction
Instruction
“fetch”ed & PC
incremented
0
M
u
x
ALU
Add result
Add
4
Instruction [31 26]
Control
Instruction [25 21]
PC
Read
address
Instruction
[31– 0]
Instruction
memory
Instruction [15 11]
Shift
left 2
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
0
M
u
x
1
PCSrc
Register
read of
source
arguments
Read
register 1
Instruction [20 16]
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
ALU ALU
result
Address
Write
data
Instruction [15 0]
Instruction
decoded
16
Instruction [5 0]
Sign
extend
Read
data
Data
memory
1
M
u
x
0
32
ALU
control
ALU op
excuted
Data written
back to
register
Datapath & Control
flow of ‘load’ instruction
lw $t1, offset($t2)
0
M
u
x
ALU
Add result
Add
4
Instruction [31– 26]
Control
Destination
register $t1
Instruction [25– 21]
PC
Read
address
Control
Instruction
Signal
[31– 0]
Instruction
“Regdest”
memory
Instruction [20– 16]
Instruction [15– 11]
rs
rt
0
M
u
x
1
Shift
left 2
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Base
register $t2
Effective
address
$t2 + offset
1
Read
register 1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
ALU ALU
result
Address
Write
data
Instruction [15– 0]
16
Instruction [5– 0]
Sign
extend
Read
data
Data
memory
1
M
u
x
0
32
ALU
control
Offset
Data to load
into $t1
Datapath & Control
flow of ‘load’ instruction
lw $t1, offset($t2)
Instruction
“fetch”ed & PC
incremented
0
M
u
x
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Instruction
[31– 0]
Instruction
memory
Instruction [15– 11]
Instruction [15– 0]
Instruction
decoded
0
M
u
x
1
1
Zero
ALU ALU
result
ALU op
excuted
Address
Shift
left 2
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Register
read of
source
argument
Read
register 1
Instruction [20– 16]
ALU
Add result
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
Base Mu
x
register
$t2
1
& offset
Write
data
16
Instruction [5– 0]
Sign
extend
32
ALU
control
Read
data
Data
memory
Write
ALU computes
data
sum value in
$t2 and offset
as address for
data memory
1
M
u
x
0
Data from
memory
written back
to register
Datapath & Control
flow of ‘branch equal’ instruction
Determine whether PC + 4 or
branch destination address is
written into the PC. MUX is set
based on the zero output of the
ALU
Instruction
“fetch”ed & PC
incremented
0
M
u
x
ALU
Add result
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Instruction
[31– 0]
Instruction
memory
Instruction [15– 11]
Shift
left 2
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Register
read of
source
arguments
Read
register 1
Instruction [20– 16]
0
M
u
x
1
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
ALU op
excuted
Zero
ALU ALU
result
Address
subtract
operation
Write
data
Instruction [15– 0]
16
Instruction [5– 0]
Sign
extend
32
ALU
control
Read
data
Data
memory
1
M
u
x
0
Datapath & Control
single cycle implementations







All previous slides have shown single cycle
implementations
Each instruction can complete within a single clock
cycle  CPI = 1
But… the clock cycle is determined by the longest
possible path in the machine.
Which is the longest instruction?
Hint: it uses 5 functional units in series: the instruction
memory, the register file, the data memory, and the
register file.
Not optimal for all instructions; must use slower clock.
Alternatives:
1. Multi-cycle implementation
2. Pipeline implementation