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Wide Input Range 1.7µW 1.2kS/s Resistive Sensor Interface Circuit with 1 cycle/sample Logarithmic Sub-Ranging Myungjoon Choi, Junhua Gu, David Blaauw, Dennis Sylvester University of Michigan, Ann Arbor, MI, myungjun@umich.edu Abstract A wide input range 1.7µW, 1.2kS/s resistive sensor interface circuit fabricated in 0.18µm CMOS is presented. This circuit consumes 6.6× lower power and 31.8× less energy than previous state-of-the-art work, considering the worst-case cycle count required for correct conversion. The proposed design uses a logarithmic subrange detector based on comparator metastability to convert an input resistance ranging from 10kΩ to 10MΩ in 1 cycle/sample. Introduction Resistive sensing is widely used in chemical [1], gas [2], and pressure sensing [3], with applications in implantable and point-of-care diagnostics among others. Sensor interface circuits for these systems are challenging due to the wide input resistance (RIN) range (kΩ to MΩ) and µW power constraint to achieve long battery life. In a resistance-to-digital converter (RDC), RIN is first converted to a voltage VIN, then measured by an ADC (Fig. 1). The resistance to voltage conversion is performed by connecting the input resistor to a fixed current source. However, accommodating a high RIN range results in one of two issues: the ADC input voltage will saturate at high RIN or an extremely high resolution ADC is required to sense low RIN that produce very small voltages. Hence, a common approach is to divide the RIN range into sub-ranges and apply different currents for each sub-range using a current DAC (I-DAC) [1,5,6]. This technique greatly increases accuracy across the total RIN range (Fig. 1). A key challenge in sub-ranging RDCs is finding the correct sub-range. Typically, the RDC starts with an arbitrary sub-range, performs a complete conversion (including ADC step), and examines the resulting code. If this code is out of range, the sub-range is changed (±1 step) and the process repeats until the correct sub-range is found [1,4]. This requires worst-case N iterations to obtain the correct code for 2N-1 sub-ranges, increasing energy and slowing the sampling rate. To address this issue, we propose a new sub-ranging RDC that finds the correct sub-range within 1 sampling cycle using a novel logarithmic converter. We also note that the energy consumed by the I-DAC is a major portion of total energy consumption. This work minimizes I-DAC energy by dynamically adjusting its on-time according to the sub-range setting, whereas previous RDCs enable the I-DAC for the worst-case stabilization time. In addition, a switched capacitor (SC) amplifier is inserted prior to the ADC; it improves ADC resolution and reduces energy via shorter VIN settling time. The proposed design consumes 1.7µW. It reduces energy per conversion by 31.8× compared to current state-of-the-art RDCs [1,2,4] and achieves 1000× RIN range with 0.21% measurement error. Logarithmic Sub-Range Detector Fig. 2 shows the logarithmic sub-range detector. The full RIN range is divided into sub-ranges that increase in geometric fashion. Hence, the correct sub-range is found by taking the log of RIN. To implement this log function, we use the intrinsic behavior of a comparator operating near its metastable point. RIN is first converted to VIN by the I-DAC, sampled on CSAMPLE and shifted up by VREF to position both VL and VR at the metastable point. At this point, φ2 switches are opened and a cross-coupled inverter pair starts to resolve VL and VR. If VIN is large, VL (VR) resolves to 1.2V (0V) quickly, while this resolution time increases exponentially as VIN becomes smaller. The subsequent inverter chains and XOR output 0 and stop the counter when VR becomes lower than VDDL/2 (mathematical analysis in Fig. 2). The proposed log converter determines the correct sub-range in one comparison, enabling 1 cycle/sample operation. To remove the effect of charge injection, the voltage transfer circuit uses bottom-plate sampling and the SC structure uses stray-capacitance insensitive topology. Auto-zeroing is also adopted for offset cancellation, resulting in offset of σ=0.24mV (40× smaller than without auto-zeroing, simulation). Across process corners, comparator gain is one-point calibrated to maintain a consistent code range. Resistance to Digital Conversion After the correct sub-range is found for a particular RIN, the corresponding I-DAC current is selected and VIN is generated from the resulting IR drop (Fig. 3). VIN is transferred to VOUT+ and VOUT- (with opposite sensitivities to VCM) via two SC amplifiers and then digitized by a 10-bit SAR ADC. The SC amplifiers are used for three reasons: 1) they perform pseudo-differential sampling to cancel out common-mode voltage; 2) they increase usable ADC output range by SC amplifier gain and thus enhance resolution by 1.98×; 3) they decouple the large capacitor DAC (CDAC+, CDAC-) from the RIN. If the large CDAC is used as the sampling capacitor, the I-DAC must remain on for a longer time due to the large RC time constant. By sampling with the smaller CSAMPLE+,- (1pF) and charging CDAC+,- (9.3pF) in a different phase, energy is reduced by 7.7× compared to an approach where CDAC+,- is used as the sampling capacitors. Fig. 4 shows the flow chart of the RDC conversion process. First, a 300nA current (IINITIAL) is applied to the unknown RIN and the resulting IINITIAL×RIN is sampled. This IINITIAL is chosen to map the entire RIN range (10kΩ – 10MΩ) to the log converter’s operating range. The log converter then produces a counter value that is compared to 4 threshold values to determine 4 coarse sub-ranges. According to the coarse sub-range, a second current (6.4µA, 1.6µA, 0.4µA, or 0.1µA) is activated on the I-DAC resulting in an ICOARSE×RIN spanning 50−800mV in each coarse sub-range. The same procedure repeats to divide each coarse sub-range into 5 fine sub-ranges, yielding 14 possible sub-ranges. Sub-ranges overlap to guarantee correct conversion for the entire RIN range. Each of the 14 fine sub-ranges specifies an I-DAC setting that ensures IFINE×RIN lies in the SC amplifier operating range. This voltage is then pseudo-differentially sampled and converted into a digital code by the 10b SAR ADC. Also, each fine sub-range specifies a sampling time, minimizing I-DAC activation time and reducing worst-case power consumption by 21%. Finally, recall that in the proposed RDC, sub-range determination is performed every conversion cycle, in contrast to traditional RDCs that can require multiple cycles to determine the correct sub-range. Measurement Results Fig. 5 shows measured log converter counter values at different VIN. Because the converter is based on metastability, it is susceptible to noise and hence ±1σ curves are shown. Each sub-range overlaps with its adjacent sub-ranges to provide error tolerance and ensure the probability of a sub-ranging failure (i.e., RIN falls outside a correct sub-range) to be < 3.2σ probability for sub-range 1 and < 5σ probability for sub-ranges 2 − 4. The worst-case measurement error is 0.21%. Off-chip 0.01% precision resistors are used to measure accuracy and the resistor bottom node voltage is swept with a sourcemeter to obtain additional equivalent resistances. The error pattern reflects repeated error behavior in each sub-range. A 10b ADC with SC amplifier shows DNL of +0.37/-0.56LSB and INL of +0.93/ -1.48LSB. The SC amplifier slightly degrades INL but improves resolution by 1.98×, resulting in better accuracy overall. At the minimum input resistance, the circuit consumes its maximum 1.7µW at a sampling rate of 1.2kS/s. Power consumption is 6.6× smaller than the state-of-the-art work in [4]. Table 1 compares the RDC with prior work showing large resistive range and similar conversion rate while worst-case energy/conversion is reduced by ~31.8×. A resistive CdS light sensor was successfully measured with the RDC (Fig. 6). Total design area is 1.5×0.82mm2 in 0.18µm CMOS (Fig. 7). References [1] Taeg Sang Cho, et al., JSSC, Feb. 2009. [2] Grassi, M., et al., JSSC, Mar. 2007. [3] Rong Wu, et al., ISSCC, 2011. [4] Hyunsoo Ha, et al., CICC, 2012. [5] Xiaoyi Mu, et al., ISCAS, 2011. [6] A. Lombardi, et al., Sensors and Actuators B 142, 2009. Previous Sample UP or DOWN (±1 step) VIN = II-DAC × RIN MULTI-STEP control signal RIN y = log(VIN) VIN R to V Converter Scale 2VIN VREF ADC Digital code Switched Cap. Amp. Logarithmic Sub-range Detector × 1 cycle/sample Φ1 Φ1Φ1 Φ2' VR VREF+VIN VREF Counter Φ1 VDDL = 0.6V VREF VREF Stray-capacitance insensitive / Autozeroing voltage transfer (VIN → VIN + VREF) CLK Logarithmic voltage to time converter based on metastability Count duration of metastable state Detect end of metastable state VL Stop Counter & Read Code VDDL/2 VR Simulated 50 100 150 Time (µs) 200 250 TT FF FS SF SS 300 250 200 150 100 Simulated 1 10 VIN (mV) 100 VR(t)–VL(t) = (VR,initial–VL,initial) × exp(αt), with α = gm/C – 1/RC Counter records when, VR(t)-VL(t) = -VDDL , count×clock period = α-1(log(VDDL)-log(VL,initial–VR,initial)) Fig. 2. A logarithmic voltage-to-time converter based on comparator metastability resolution time, and its transient voltage behavior and sub-ranging code output vs. VIN. Φ1 CSAMPLEΦ1 VCM Φ1' Φ2 Φ2' Φ2 VOUTΦ1 0.0 -0.5 -1.0 -1.5 Simulated 0.0 0.2 0.4 0.6 VIN(V) 0.8 1.0 ADC Output Code VOUT+ - VOUT- (V) 0.5 VOUT- (= VREF2+VCM –VIN) VDDH CDACVCM GND 800 400 50 0.4 0.2 0.0 -0.2 -0.4 -0.6 200 300 400 500 600 700 800 900 40 30 20 10 0 100 10 0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 VIN (mV) Code 1.0 0.5 0.0 -0.5 -1.0 -1.5 200 300 400 500 600 700 800 900 Code 100 10 1,000 10,000 Input Resistance (kΩ) 100 300 1000 100 90 80 70 60 50 40 30 20 10 Illuminance (Lux) Room light condition 0 1000 2000 3000 Time (ms) 0.0 0.2 0.4 0.6 0.8 VIN(V) 5000 This work CICC 2012 [4] Technology (µm) Required number of cycle (worst case) 0.18 0.13 0.5 1 4 N/A Supply (V) 1.2/0.6 10k – 10M 1,000 1.2 < 0.21 0.5 23k – 4.6M 200 1 1.42 45.2 N/A 87.4 > 60** N/A 1.7 11.3 66 32 6,000 10,000 Input Range (Ω) Conv. Rate (kS/s) Meas. Error (%) Measured 0 4000 Fig. 6. Conversion result measured with off-the-shelf CdS light sensor. < 0.32 ISCAS JSSC 2011 [5] 2009 [1] JSSC 2007 [2] Sensors and Actuators B 142 2009 [6] 0.18 0.35 0.35 5 6, (5 cycles with coarse ADC) 3.3 1.2/0.5 60k – 10M 10k – 9M 166.7 900 1.83 N/A < 1.32 N/A 3.3 100 – 20M 200,000 0.1 < 0.14 1.0 1.2 Fig. 3. (a) A switched capacitor amplifier that pseudo-differentially samples input and (b) improvement of ADC resolution by SC amplifier gain. 8 N/A 10k – 2G 200,000 N/A < 2.7 * Assumes a worst case cycle count and minimum input resistance. ** Coarse ADC power is not reported, thus extra energy needed for finding sub-range is not included. 0.42mV/code 200 (b) 60 Max. R / Min. R VOUT- 1.15mV/code 0.58mV/code 600 1.2 70 Energy/conversion (nJ) (worst case)* Power (µW) CSAMPLE/CT = 3 CSAMPLE/CT = 2 CSAMPLE/CT = 1 1000 Average Average ± 1σ TABLE I. Performance summary and comparison. ADC CT (a) CSAMPLE/CT = 3 CSAMPLE/CT = 2 CSAMPLE/CT = 1 1.0 Φ1 SAR ADC VOUT+ (= VREF1–VCM +VIN) VCM Φ1 VREF2 1.5 CDAC+ VOUT+ GND VOUT+ VCM VREF1 VIN VDDH CT Φ1 Φ1 Φ2' GND Φ1 Φ2 Φ1' RIN VDDH Φ2 CSAMPLE+ VIN Pseudo-Differentially sample & amplify VIN Fig. 5. Measured results of a sub-ranging, DNL & INL of 10b ADC with SC amplifier, and measurement error for input resistance range. 50 0 Similar to ICOARSE search, Choose 1 of 14 IFINE based on Code & RC lly ua d ad an gr h or by ns ed Se ver co 0 Sub-ranging code VIN = 100mVVIN = 10mV VIN = 1mV Start Comparison Voltage(V) Φ1', Φ2' are delayed versions of Φ1, Φ2, respectively. 1.2 1.0 0.8 0.6 0.4 0.2 0.0 RC = 4 ICOARSE = 0.1µA Code value? 10b SAR ADC 80 Sub-ranging code Φ2 Φ2 V L RC = 3 ICOARSE = 0.4µA Logarithmically convert VIN to sub-ranging code IFINE×RIN Pseudo Differential Sampling 90 Meas. Error (%) VIN Φ1 RC = 2 ICOARSE = 1.6µA Fig. 4. Conversion process flow chart of 1 sample. RIN is logarithmically compressed, sub-ranged, then converted by 10b ADC. Sub-ranging code VREF = 0.6V Coarse Sub range(RC) = 1 ICOARSE = 6.4µA Next Sample Measured Resistance (Ω) VDDH = 1.2V Φ2 CSAMPLE Φ2 Logarithmic Sub-range search Proposed Approach Fig. 1. An overview of N cycles/sample conventional RDC and a proposed 1 cycle/sample RDC with logarithmic sub-range detector. Φ1' ICOARSE×RIN Sampling I-DAC control code RIN Conventional System 3 < Code < 14 ? Code value? 44 < Code < 61? 14 < Code < 44 ? Code > 61? 100k Current DAC (I-DAC) Logarithmically convert VIN to sub-ranging code Logarithmic Sub-range search DNL (LSB) control signal .. Digital code IINITIAL×RIN Sampling INL (LSB) Yes Conversion Process Flow * 2N-1 = Number of total sub-ranges 30k RIN × N cycles/sample* No In range? ADC 10k R to V VIN Converter RIN Flow IINITIAL(0.3µA) and Sample Scan for testing FSM Sub-ranging circuit I-DAC Decap SAR ADC Fig. 7. Microphotograph (1.5 × 0.82mm2).