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SN74LV4046A
SCES656D – FEBRUARY 2006 – REVISED SEPTEMBER 2015
SN74LV4046A High-Speed CMOS Logic Phase-Locked Loop With VCO
1
1 Features
•
•
•
•
•
•
•
Choice of Three Phase Comparators
– Exclusive OR
– Edge-Triggered J-K Flip-Flop
– Edge-Triggered RS Flip-Flop
Excellent VCO Frequency Linearity
VCO-Inhibit Control for ON/OFF Keying and for
Low Standby Power Consumption
Optimized Power-Supply Voltage Range From 3 V
to 5.5 V
Wide Operating Temperature Range . . . –40°C to
125°C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
The signal input can be directly coupled to large
voltage signals, or indirectly coupled (with a series
capacitor) to small voltage signals. A self-bias input
circuit keeps small voltage signals within the linear
region of the input amplifiers. With a passive lowpass filter, the SN74LV4046A forms a second-order
loop PLL. The excellent VCO linearity is achieved by
the use of linear operational amplifier techniques.
Various applications include telecommunications,
digital phase-locked loop and signal generators.
Device Information(1)
PART NUMBER
SN74LV4046A
BODY SIZE (NOM)
SOP (16)
7.70mm x 10.20mm
SOIC (16)
6.00mm x 9.90mm
TSSOP (16)
6.40mm x 5.00mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SN74LV4046A Functional Block Diagram
VCC
2 Applications
•
•
•
PACKAGE
16
Telecommunications
Signal Generators
Digital Phase-Locked Loop
Phase
Comparator
1
2
13 PC2OUT
3
Phase
Comparator
2
15 PC3OUT
VCOIN
9
Phase
Comparator
3
INH
5
PC1OUT
3 Description
The SN74LV4046A is a high-speed silicon-gate
CMOS device that is pin compatible with the
CD4046B and the CD74HC4046. The device is
specified in compliance with JEDEC Std 7.
The SN74LV4046A is a phase-locked loop (PLL)
circuit that contains a linear voltage-controlled
oscillator (VCO) and three different phase
comparators (PC1, PC2, and PC3). A signal input
and a comparator input are common to each
comparator.
SIGIN 14
COMPIN
C1A
6
C1B
7
1
4
Voltage
Controlled
Oscillator
PCPOUT
VCOOUT
10 DEMOUT
R1 11
R2 12
8
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LV4046A
SCES656D – FEBRUARY 2006 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 14
11 Device and Documentation Support ................. 15
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
12 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2007) to Revision D
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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5 Pin Configuration and Functions
D, DGV, NS, or PW Package
16-Pin SOIC, SOP, or TSSOP
Top View
PCPOUT
PC1OUT
COMPIN
VCOOUT
INH
C1A
C1B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
PC3OUT
SIGIN
PC2OUT
R2
R1
DEMOUT
VCOIN
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
PCPOUT
1
O
Phase comparator pulse output
PC1OUT
2
O
Phase comparator 1 output
COMPIN
3
I
Comparator input
VCOOUT
4
O
VCO output
INH
5
I
Inhibit input
C1A
6
—
Capacitor C1 connection A
C1B
7
—
Capacitor C1 connection B
GND
8
—
Ground (0 V)
VCOIN
9
I
VCO input
DEMOUT
10
O
Demodulator output
R1
11
—
Resistor R1 connection
R2
12
—
Resistor R2 connection
PC2OUT
13
O
Phase comparator 2 output
SIGIN
14
I
Signal input
PC3OUT
15
O
Phase comparator 3 output
VCC
16
—
Positive supply voltage
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6 Specifications
6.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
DC supply voltage
–0.5
7
V
VI
Input voltage
–0.5
VCC + 0.5
V
VO
Output voltage
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output curent
VO = 0 to VCC
±35
mA
ICC
DC VCC or ground current
±70
mA
TJ
Junction temperature
Tstg
Storage temperature
(1)
150
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
TA
Operating free-air temperature
–40
125
°C
VCC
Supply voltage
3
5.5
V
VI, VO
DC input or output voltage
0
VCC
V
6.4 Thermal Information
THERMAL METRIC (1)
RθJA
(1)
4
Junction-to-ambient thermal resistance
D
DGV
NS
PW
16 PINS
16 PINS
16 PINS
16 PINS
73
120
64
108
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
PARAMETER
VI (V)
IO (mA)
VCC (V)
MIN
3 to 3.6
VCC × 0.7
4.5 to 5.5
VCC × 0.7
TYP
MAX
UNIT
VCO
VIH
High-level input voltage
INH
VIL
Low-level input voltage
INH
VOH
High-level
output voltage
VCOOUT
VOL
Low-level
output voltage
VCOOUT
CMOS
VIL or VIH
TTL
–12
CMOS
0.05
VIL or VIH
TTL
C1A, C1B
(test purposes only)
II
Input leakage current
–0.05
INH, VCOIN
V
3 to 5.5
VCC × 0.3
4.5 to 5.5
VCC × 0.3
3 to 3.6
VCC – 0.1
4.5 to 5.5
VCC – 0.1
4.5 to 5.5
3.8
V
3 to 3.6
0.1
4.5 to 5.5
0.1
12
4.5 to 5.5
0.55
12
4.5 to 5.5
0.65
VCC or GND
μA
50
kΩ
3
50
kΩ
40
No Limit
3 to 5.5
R2 range (1)
3 to 5.5
3 to 3.6
4.5 to 5.5
40
No Limit
3 to 3.6
1.1
1.9
4.5 to 5.5
1.1
3.2
Operating voltage range
Over the range specified for
R1 for linearity (2)
VCOIN
V
±1
5.5
R1 range (1)
C1 capacitance range
V
3
pF
V
PHASE COMPARATOR
VIH
DC-coupled high-level
input voltage
SIGIN,
COMPIN
VIL
DC-coupled low-level input voltage
VOH
High-level
output voltage
VOL
Low-level
output voltage
PCPOUT,
PCNOUT
PCPOUT,
PCNOUT
SIGIN,
COMPIN
3 to 3.6
VCC × 0.7
4.5 to 5.5
VCC × 0.7
3 to 3.6
VCC × 0.3
4.5 to 5.5
VCC × 0.3
–0.05
3 to 5.5
VCC – 0.1
–6
3 to 3.6
2.48
TTL
–12
4.5 to 5.5
3.8
CMOS
0.02
CMOS
VIL or VIH
VIL or VIH
4
TTL
V
3 to 3.6
0.1
4.5 to 5.5
0.1
4.5 to 5.5
0.4
3 to 3.6
±11
4.5 to 5.5
±29
II
Input leakage current
SIGIN,
COMPIN
IOZ
3-state off-state current
PC2OUT
VIL or VIH
Input resistance
SIGIN,
COMPIN
VI at self-bias operating
point, VI = 0.5 V
3
800
4.5
250
RS > 300 kΩ, Leakage
current can influence
VDEMOUT
3 to 3.6
50
300
4.5 to 5.5
50
300
VI = VVCOIN = VCC/2, Values
taken over RS range
3 to 3.6
±30
4.5 to 5.5
±20
RI
VCC or GND
V
3 to 5.5
±5
V
μA
μA
kΩ
DEMODULATOR
RS
Resistor range
VOFF
Offset voltage VCOIN to VDEM
ICC
Quiescent device current
(1)
(2)
Pins 3, 5, and 14 at VCC,
Pin 9 at GND, II at pins 3
and 14 to be excluded
5.5
kΩ
mV
50
μA
The value for R1 and R2 in parallel should exceed 2.7 kΩ.
The maximum operating voltage can be as high as VCC – 0.9 V; however, this may result in an increased offset voltage.
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted) CL = 50 pF, Input tr, tf = 6 ns
PARAMETER
VCC
(V)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PHASE COMPARATOR
tPLH, tPHL
Propagation delay
SIGIN, COMPIN to
PC1OUT
3 to 3.6
135
4.5 to 5.5
50
tPLH, tPHL
Propagation delay
SIGIN, COMPIN to
PCPOUT
3 to 3.6
300
4.5 to 5.5
60
tPLH, tPHL
Propagation delay
SIGIN, COMPIN to
PC3OUT
3 to 3.6
200
4.5 to 5.5
50
tTHL, tTLH
Output transition time
tPZH, tPZL
3-state output enable time
SIGIN, COMPIN to
PC2OUT
tPHZ, tPLZ
3-state output disable time
SIGIN, COMPIN to
PC2OUT
AC-coupled input sensitivity
(P-P) at SIGIN or
COMPIN
VI(P-P)
3 to 3.6
75
4.5 to 5.5
15
3 to 3.6
270
4.5 to 5.5
54
3 to 3.6
320
4.5 to 5.5
65
3 to 3.6
11
4.5 to 5.5
15
ns
ns
ns
ns
ns
ns
mV
VCO
Δf/ΔT
Frequency stability with temperature change
fMAX
Maximum frequency
Center frequency (duty 50%)
ΔfVCO
VI = VCOIN = 1/2 VCC,
R1 = 100 kΩ,
R2 = ∞,
C1 = 100 pF
C1 = 50 pF,
R1 = 3.5 kΩ,
R2 = ∞
C1 = 0 pF,
R1 = 9.1 kΩ,
R2 = ∞
C1 = 40 pF,
R1 = 3 kΩ,
R2 = ∞,
VCOIN = VCC/2
3 to 3.6
0.11
4.5 to 5.5
0.11
3 to 3.6
24
4.5 to 5.5
24
3 to 3.6
38
4.5 to 5.5
38
3 to 3.6
4.5 to 5.5
4.5 (1)
7
10
12
17
15 (1)
%/°C
MHz
MHz
17.5 (1)
C1 = 100 pF,
R1 = 100 kΩ,
R2 = ∞
3 to 3.6
0.4%
Frequency linearity
4.5 to 5.5
0.4%
Offset frequency
C1 = 1 nF,
R2 = 220 kΩ
3 to 3.6
400
4.5 to 5.5
400
kHz
DEMODULATOR
VOUT vs fIN
(1)
6
C1 = 100 pF,
C2 = 100 pF,
R1 = 100 kΩ,
R2 = ∞,
R3 = 100 kΩ
3
4.5
8
330
mV/kHz
Data is specified at 25°C
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SIGIN
COMPIN
VCOOUT
PC1OUT
VCC
VCOIN
GND
Loop Locked at fo
Figure 1. Typical Waveforms for PLL Using
Phase Comparator 1
SIGIN
COMPIN
VCOOUT
VCC
GND
PC2 OUT
High-Impedance Off State
VCO IN
PCPOUT
Loop Locked at fo
Figure 2. Typical Waveforms for PLL Using
Phase Comparator 2
SIGIN
COMPIN
VCOOUT
PC3OUT
VCC
VCOIN
GND
Loop Locked at fo
Figure 3. Typical Waveforms for PLL Using
Phase Comparator 3
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SIGIN, COMPIN
Inputs
VS
tPHL
PCPOUT, PC1OUT,
PC3OUT
Outputs
tPLH
VS
tTHL
tTLH
Figure 4. Input-to-Output Propagation Delays and
Output Transition Times
SIGIN
Inputs
VS
COMPIN
Inputs
VS
tPHZ
tPZL
tPZH
PC2OUT
Output
tPLZ
90%
VS
10%
Figure 5. 3-State Enable and Disable Times for PC2OUT
8
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6.7 Typical Characteristics
VCC
VCC
VDEMOUT (AV)
VDEMOUT (AV)
1/2 V CC
1/2 V CC
0
φDEMOUT
–360°
0°
Phase Comparator 1:
VDEMOUT = VPC1OUT = (VCC/π) (SIGIN – COMPIN);
DEMOUT = (SIGIN – COMPIN)
360°
Figure 6. Average Output Voltage vs Input Phase Difference
0
φDEMOUT
–360°
0°
Phase Comparator 2:
VDEMOUT = VPC2OUT = (VCC/4) (SIGIN – COMPIN);
DEMOUT = (SIGIN – COMPIN)
360°
Figure 7. Average Output Voltage vs Input Phase Difference
VCC
VDEMOUT(AV)
1/2 VCC
0
0°
180° φDEMOUT
360°
Phase Comparator 3:
VDEMOUT = VPC3OUT = (VCC/2π) (SIGIN – COMPIN);
DEMOUT = (SIGIN – COMPIN)
Figure 8. Average Output Voltage vs Input Phase Difference
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7 Detailed Description
7.1 Overview
The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the
CD74HC4046. The device is specified in compliance with JEDEC Std 7.
The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO)
and three different phase comparators (PC1, PC2, and PC3) as explained in the Features section. A signal input
and a comparator input are common to each comparator as shown in the Functional Block Diagram.
The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input
amplifiers. With a passive lowpass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO
linearity is achieved by the use of linear operational amplifier techniques. Various applications include
telecommunications, Digital Phase Locked Loop and Signal generators.
The VCO requires one external capacitor C1 (between C1A and C1B) and one external resistor R1 (between R1
and GND) or two external resistors R1 and R2 (between R1 and GND, and R2 and GND). Resistor R1 and
capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency
offset if required. The high input impedance of the VCO simplifies the design of lowpass filters by giving the
designer a wide choice of resistor or capacitor ranges. In order not to load the lowpass filter, a demodulator
output of the VCO input voltage is provided at pin 10 (DEMOUT). In contrast to conventional techniques where the
DEMOUT voltage is one threshold voltage lower than the VCO input voltage, here the DEMOUT voltage equals that
of the VCO input. If DEMOUT is used, a load resistor (RS) should be connected from DEMOUT to GND; if unused,
DEMOUT should be left open. The VCO output (VCOOUT) can be connected directly to the comparator input
(COMPIN), or connected through a frequency divider. The VCO output signal has a specified duty factor of 50%.
A LOW level at the inhibit input (INH) enables the VCO and demodulator, while a HIGH level turns both off to
minimize standby power consumption.
7.2 Functional Block Diagram
VCC
16
Phase
Comparator
1
2
13 PC2OUT
3
Phase
Comparator
2
15 PC3OUT
VCOIN
9
Phase
Comparator
3
INH
5
SIGIN 14
COMPIN
C1A
6
C1B
7
1
4
Voltage
Controlled
Oscillator
PC1OUT
PCPOUT
VCOOUT
10 DEMOUT
R1 11
R2 12
8
GND
10
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7.3 Feature Description
There are three choices for the Phase Comparators in this device which are listed as below:
• Phase comparator 1 (PC1) is an Exclusive OR network. The average output voltage from PC1, fed to VCO
input through the low pass filter and seen at the demodulator output at pin 10 (VDEMOUT), is the resultant of
the phase differences of signals (SIGIN) and the compartor input (COMPIN) as shown in Figure 7. The
average of V DEM is equal to 1/2 VCC when there is no signal or noise at SIGIN, and with this input the VCO
oscillates at the center frequency (fo).
• Phase comparator 2 (PC2) is an Edge-Triggered Flip-Flop. This is a positive edge-triggered phase and
frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions
and the duty factors of SIGIN and COMPIN are not important. PC2 comprises two D-type flip-flops, controlgating and a three-state output stage. The circuit functions as an up-down counter where SIGIN causes an upcount and COMPIN a down-count. The average output voltage from PC2, fed to the VCO through the lowpass
filter and seen at the demodulator output at pin 10 (VDEMOUT), is the resultant of the phase differences of
SIGIN and COMPINas in Figure 8.
• Phase comparator 3 (PC3) is an positive Edge-Triggered RS Flip-Flop. This is a positive edge-triggered
sequential phase detector using an RS-type flip-flop. When the PLL is using this comparator, the loop is
controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. The
average output from PC3, fed to the VCO through the lowpass filter and seen at the demodulator at pin 10
(VDEMOUT), is the resultant of the phase differences of SIGIN and COMPIN as shown in Figure 9.
The excellent VCO linearity is achieved by the use of linear operational amplifier techniques. It has low standby
power consumption using VCO inhibit control. Wide operating temperature range from –40°C to 125°C along with
an optimized power supply voltage range from 3 V to 5.5 V.
7.4 Device Functional Modes
The SN74LV4046A device does not feature any special functional modes.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The most common use for the digital phased-locked loop (PLL) device is to match the VCO output to the same
phase as the incoming signal and produce an error signal (DEMOUT) that indicates the amount of phase shift
required for the match. This can be used as part of many complex systems.
8.2 Typical Application
VCC
16
SIGIN
Input
COMPIN
VCOOUT
INH
C1A
C1
C1B
R1
R2
R1
R2
14
3
4
Phase
Comparator
1
2
Phase
Comparator
2
13
Phase
Comparator
3
5
6
7
1
15
9
Voltage
Controlled
Oscillator
10
PC1OUT
PC2OUT
R3
PCPOUT
C2
PC3OUT
VCOIN
DEMOUT
R5
11
12
8
GND
Figure 9. SN74LV4046A Digital Clock Signal Phase Comparison Application
12
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Typical Application (continued)
8.2.1 Design Requirements
Table 1 and Table 2 lists the design requirements of the SN74LV4046A.
Table 1. Component Selection Criteria (1)
(1)
COMPONENT
VALUE
R1
3 kΩ to 50 kΩ
R2
3 kΩ to 50 kΩ
R1 || R2
> 2.7 kΩ
C1
> 40 pF
R3
1 kΩ
C2
1 uF
R5
50 kΩ to 300 kΩ
R1 between 3 kΩ and 50 kΩ
R2 between 3 kΩ and 50 kΩ
R1 + R2 parallel value > 2.7 kΩ
C1 > 40 pF
Table 2. CPD (1)
CHIP SECTION
CPD
Comparator 1
120
VCO
120
(1)
UNIT
pF
R1 between 3 kΩ and 50 kΩ
R2 between 3 kΩ and 50 kΩ
R1 + R2 parallel value > 2.7 kΩ
C1 > 40 pF
8.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– VIH and VIL for each input can be found in Electrical Characteristics.
2. Recommended Output Conditions:
– Valid load resistor values are specified in Electrical Characteristics.
3. Frequency Selection Criterion:
– Frequency data is found in Electrical Characteristics.
8.2.3 Application Curves
Table 3 lists the application curves in the Typical Characteristics section.
Table 3. Table of Graphs
GRAPH TITLE
FIGURE
Average Output Voltage vs Input Phase Difference
Figure 6
Average Output Voltage vs Input Phase Difference
Figure 7
Average Output Voltage vs Input Phase Difference
Figure 8
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SN74LV4046A
SCES656D – FEBRUARY 2006 – REVISED SEPTEMBER 2015
www.ti.com
9 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage ratings located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply. a 0.1-µF capacitor is recommended and if there are multiple VCC pins then 0.01-µF or 0.022-µF capacitor
is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies
of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass capacitor should be installed as
close to the power pin as possible for best results.
10 Layout
10.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight
and therefore some traces must turn corners. Figure 10 shows progressively better techniques of rounding
corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.
10.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 10. Trace Example
14
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Product Folder Links: SN74LV4046A
SN74LV4046A
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SCES656D – FEBRUARY 2006 – REVISED SEPTEMBER 2015
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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15
PACKAGE OPTION ADDENDUM
www.ti.com
8-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV4046AD
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV4046A
SN74LV4046ADG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV4046A
SN74LV4046ADGVR
ACTIVE
TVSOP
DGV
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW046A
SN74LV4046ADR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV4046A
SN74LV4046ADRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV4046A
SN74LV4046AN
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74LV4046AN
SN74LV4046ANE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74LV4046AN
SN74LV4046ANS
ACTIVE
SO
NS
16
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
74LV4046A
SN74LV4046ANSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
74LV4046A
SN74LV4046APW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW046A
SN74LV4046APWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW046A
SN74LV4046APWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW046A
SN74LV4046APWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW046A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Sep-2015
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN74LV4046ADGVR
TVSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
8.0
12.0
Q1
DGV
16
2000
330.0
12.4
6.8
4.0
1.6
W
Pin1
(mm) Quadrant
SN74LV4046ADR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV4046ANSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74LV4046APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV4046ADGVR
TVSOP
DGV
16
2000
367.0
367.0
35.0
SN74LV4046ADR
SOIC
D
16
2500
333.2
345.9
28.6
SN74LV4046ANSR
SO
NS
16
2000
367.0
367.0
38.0
SN74LV4046APWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
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