Download Analog Integrated Circuits Lecture 1: Introduction and MOS Physics

Analog Integrated Circuits
Lecture 1: Introduction and MOS
Physics
ELC 601 – Fall 2013
Dr. Ahmed Nader
Dr. Mohamed M. Aboudina
[email protected]
[email protected]
Department of Electronics and Communications Engineering
Faculty of Engineering – Cairo University
2
MOS: Subthreshold (Weak Inversion)
• Subthreshold Conduction:
For VGS near VTH, ID has an exponential dependence on VGS:
Max transconductance efficiency
Used for low currents & low frequency applications
5/4/2017
© Ahmed Nader, 2013
3
MOS: Intrinsic Capacitance
•
•
•
•
C1 is the gate-channel capacitance
C2 is the channel-bulk depletion capacitance
C3 & C4 is the overlap gate-source(drain) capacitance
C5 & C6 is the source/drain –bulk junction capacitance (bottomplate and sidewall)
Note that junction capacitors are voltage-dependent (non-linear)
5/4/2017
© Ahmed Nader, 2013
4
MOS: Intrinsic Capacitance
5/4/2017
© Ahmed Nader, 2013
5
MOS Device as a Capacitor: Varactor
Assignment 1a:
There is a special device with n-doping in
an NWELL. Plot the characteristics of such
a device. Comment on its properties.
5/4/2017
© Ahmed Nader, 2013
6
Small Signal Model
• The slope of the diode characteristic at the
Q-point is called the diode conductance
and is given by:
gd 
gd 
iD
v D
ID
VT
Q  point


IS
VD  ID  IS

 exp 
VT
VT
VT 
ID
0.025V
 40ID for ID  IS
• gd is small but non-zero for ID = 0 because

slope of diode equation is nonzero at the
origin.
1
r

• Diode resistance is given by:
d
gd
5/4/2017
© Ahmed Nader, 2013

7
Small Signal Operation of a Diode



S



 v  
 V  v  

iD  I exp D  1
I D  id  I S exp D d  1

 V  
 V
 

T
T
  

 


2
3

 V  
 V   v
v 
v 







1
1
I D  id  I S exp D  1  I S exp D  d   d    d   ...

 V  V
2 VT  6 VT 

 V  
 T   T


 T 

Subtracting ID from both sides of the equation,


d
S 
 T

2
3

v 1 vd  1 vd 

id (ID  I )       ...
V 2 VT  6 VT 


For id to be a linear function of signal voltage vd , vd  2VT  0.05V or vd  5 mV
 requirement for small-signal operation of the diode.
This represents the


 d 
S 

 T 
id (ID  I )
5/4/2017

v
= gdvd  iD  ID  gdvd
V
© Ahmed Nader, 2013
8
Current Controlled Attenuator
Magnitude of ac voltage vo developed
across diode can be controlled by value
of dc bias current applied to diode.
From ac equivalent circuit,
From dc equivalent circuit ID = I,
For RI = 1 kW, IS = 10-15 A,
r
1
 vi
r R
R
1 I
rd
1
vo  v
i (I  I )R
S
I
1
VT




d
i 

 d
I 
vo  v

If I = 0, vo = vi, magnitude of vi is
limited to only 5 mV.
If I = 100 mA, input signal is
attenuated by a factor of 5, and vi
can have a magnitude of 25 mV.
5/4/2017
© Ahmed Nader, 2013
9
Small-Signal Model of a MOS (Two-Port Model)
y11 
y12 
Using 2-port y-parameter network,
ig  y11vgs  y12vds
id  y21vgs  y22vds
y21 
The port variables can represent either

time-varying
part of total voltages and
currents or small changes in them away
from Q-point values.

5/4/2017
y22 
ig
v gs

v
ds
0
ig
v ds
gs
0
id
v gs

v
ds
0
id
v ds
vGS

v

v
gs
0
iG
0
Q  point
iG
v DS
0
Q  point
iD
vGS
2ID
VGS VTN

ID
Q  point
iD
v DS

Q  point
1

VDS
10
Small-Signal Model of a MOS
Transconductance:
gm  y21 
• Since gate is insulated from
channel by gate-oxide input
resistance of transistor is infinite.
• Small-signal parameters are
controlled by the Q-point.
• For same operating point, MOSFET
has lower transconductance and
lower output resistance that BJT.
5/4/2017

2I D
VGS VTN
 2K n I D
Output resistance:
ro 
1
1

y22 I D
11
MOS Transistor
Gain Vs. Voltage Swing
Important Trade-Offs!!
Gain Vs. Speed
Gain Vs. Current
5/4/2017
© Ahmed Nader, 2013
12
MOS Transistor
Small Signal Model: Body Effect
Drain current depends on threshold voltage which in
turn depends on vSB. Back-gate transconductance
is:
gmb 
iD
v BS

Q  point
iD
v SB
Q  point
 i V 
gmb  D  TN 
(gm) gm
V v 
 TN  SB Q  point
0 <  < 1 is called back-gate tranconductance
parameter.
5/4/2017
© Ahmed Nader, 2013
13
Small-Signal Model of a MOS: High Frequency Model
• Voltage dependent current source (gmVgs) models dependence of
drain current on gate-source voltage
• Output resistance models dependence of drain current on drainsource voltage (channel length modulation)
• Voltage dependent current source (gmbVbs) models dependence of
drain current on bulk-source voltage (body effect)
5/4/2017
© Ahmed Nader, 2013
14
MOS Transistor
Useful Model
• Small Signal:
+
-
5/4/2017
© Ahmed Nader, 2013
15
MOS Transistor
Special Cases
Bias point
5/4/2017
© Ahmed Nader, 2013
16
Deep Sub-Micron Technologies
5/4/2017
© Ahmed Nader, 2013
17
Fixed for the
technology and
fixed L
Low-voltage – HighSpeed trade-off
5/4/2017
© Ahmed Nader, 2013
18
Deep Sub-Micron Technologies
Some small geometry effects:
1- Gate leakage
2- Threshold voltage variation
3- Output impedance variation with VDS (non-linearity)
4- Mobility degradation with vertical field
5- Velocity saturation
6- Reliability Effects (GO, Hot Carrier, NBTI, ..)
7- Stress Effects (STI, Well Proximity, ..)
Assignment 1b:
Choose one of those effects in 6 or 7 and describe it
in details (physical meaning, effect on performance, etc.)
5/4/2017
© Ahmed Nader, 2013
19
Deep Sub-Micron Technologies
What about scaling of Vth?
5/4/2017
© Ahmed Nader, 2013
20
Deep Sub-Micron Technologies – Mobility degradation with Vertical Field
• Carriers are confined to a narrower region below oxidesilicon interface leading to more carrier scattering and hence
lower mobility
Assignment 1c:
Find an expression for HD3
5/4/2017
© Ahmed Nader, 2013
21
Deep Sub-Micron Technologies – Velocity Saturation
5/4/2017
© Ahmed Nader, 2013
22
Deep Sub-Micron Technologies – Velocity Saturation
5/4/2017
© Ahmed Nader, 2013
23
MOS Device Models
Level 3 Model
BSIM (Berkeley Short-Channel IGFET Model)
5/4/2017
© Ahmed Nader, 2013
24
MOS Device Models
5/4/2017
© Ahmed Nader, 2013
25
Analog Layout
5/4/2017
© Ahmed Nader, 2013
26
Analog Layout
5/4/2017
© Ahmed Nader, 2013
27
Analog Layout
5/4/2017
© Ahmed Nader, 2013
28
Analog Layout
Adding Dummies. How can dummies help in STI?
Connect gate (poly) from both sides
5/4/2017
© Ahmed Nader, 2013
29
Analog Layout: Inter-digitation
5/4/2017
© Ahmed Nader, 2013
30
Analog Layout
5/4/2017
© Ahmed Nader, 2013
31
Analog Layout: Common Centroid
5/4/2017
© Ahmed Nader, 2013
32
Analog Layout
5/4/2017
© Ahmed Nader, 2013
33
Resistor Layout
5/4/2017
© Ahmed Nader, 2013
34
Capacitor Layout
5/4/2017
© Ahmed Nader, 2013
35
Inductor Layout
5/4/2017
© Ahmed Nader, 2013
36
Inductor Layout
Spiral Inductor Calculator (Stanford): http://www-smirc.stanford.edu/spiralCalc.html
Assignment1: Using ASITIC tool: http://rfic.eecs.berkeley.edu/~niknejad/doc-05-26-02/asitic.html
Design an Inductor with L=2nH and Q>10
5/4/2017
© Ahmed Nader, 2013
37
Analog Layout: Summary
5/4/2017
© Ahmed Nader, 2013
38
Analog Layout: Example
5/4/2017
© Ahmed Nader, 2013
39
Analog Layout: Example
5/4/2017
© Ahmed Nader, 2013